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Chapter 4

CMOS Process Technology


Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory July 5th, 2004; Revised - June 26th, 2006

B.Supmonchai

Outlines

Chip-Making Process Photolithography CMOS IC Fabrication Processes


Simple Process

Modern Process

Packaging Technology

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Chip-Making Process: An Overview


Photolithography

Crystal Growth

Packaging

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Growing the Silicon Ingot

Most common technique is the Czochralski (CZ) method developed by Mitsubishi Materials Silicon in the 50s
Length: up to 2 m

Diameter: 200 mm (8) to

300 mm (12)

Weight: Over 225 kg. Pulling takes up to hundred

hours

From Smithsonian, 2000

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Czochralski (CZ) Method


1420 C

Develop by Mitsubishi in the 50s


Crystal orientation is determined by seed orientation Ingot diameter is determined by temperature, orientation, and extraction speed.
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Wafer Shaping
Ingot is cut around and ground down into a uniform diameter (8-12), then sliced into wafers of about 1 mm thick.

Q ui c kTi m e and a TI FF (U ncom p r essed) decompr esso r ar e n eeded to see t hi s pi ctur e.

Wire Saw Machine

The sliced wafers are mechanically lapped by the use of alumina abrasive material to remove surface roughness and damages caused by the saw cut and to improve the flatness of the wafer.
Q ui c kTi m e and a TI FF (U ncom p r essed) decompr esso r ar e n eeded to see t hi s pi ctur e.

Lapping Machine
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Wafer Shaping (2)


Mechanical damages induced during the previous processes are removed by chemical etching.

The mechano-chemical polishing process improves the flatness of the wafer, making highly flat surface by the use of colloidal silica.

Q ui c kTi m e and a TI FF (U ncom p r essed) decompr esso r ar e n eeded to see t hi s pi ctur e.

Wafer Polishers
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The Target: CMOS Inverter


N Well

VDD
PMOS

VDD 2l

PMOS
In Out
In Out

Contacts

Metal 1

NMOS

Polysilicon

Schemetic

NMOS GND

Layout

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Current CMOS Structure

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CMOS Process at a Glance


Define active areas Etch and fill trenches

One full photolithography sequence per layer (mask)


Built (roughly) from the bottom up
5 metal 2 4 metal 1 2 polysilicon

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

3 source and drain diffusions


1 tubs (aka wells, active areas)

Create contact and via windows Deposit and pattern metal layers

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Planarization: Polishing the Wafers

liquid carrier with a suspended abrasive component such as aluminum oxide or silica

From Smithsonian, 2000

CMP (Chemical-Mechanical Planarization) - Essential to keep the surface of the wafer approximately flat between processing steps.
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Outlines

Chip-Making Process Photolithography CMOS IC Fabrication Processes


Simple Process

Modern Process

Packaging Technology

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Photolithography

An IC consists of several layers of material that are manufactured in successive steps.


Photo + Litho + Graphy = Writing Stone with Light
(Light) (Stone) (Writing)

Photolithography is used to selectively process the layers, where the 2-D mask geometry is copied on the surface.
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Photolithographic Process
oxide growth optical mask

stepper exposure

photoresist removal (ashing)

photoresist coating

Typical operations in a single photolithographic process


Ion implantation Plasma etching Metal deposition process step photoresist development spin, rinse, dry
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Oxide Growth/Oxide Deposition

Oxidation of the silicon surface creates a SiO2 layer that acts as an insulator. Oxide layers are also used to isolate metal interconnections.

An annealing step is required to restore the crystal structure after thermal oxidation.

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Photoresist Deposition/Coating

The surface of the wafer is coated with a photosensitive material, the photoresist. The mask pattern is developed on the photoresist, with UV light exposure.

Depending on the type of the photoresist (negative or positive), the exposed or unexposed parts of the photoresist change their property and become resistant to certain types of solvents.
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Stepper Exposure
A Mask Sample

Glass Mask (reticle) containing the patterns to be transferred is brought in close proximity to the wafer

The mask pattern is developed on the photoresist, with UV light exposure.


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Photoresist Devolopment

The wafers are developed in either an acid or base solution to remove the nonexposed (exposed) areas of the photoresist. Once the exposed photoresist is removed, the wafer is soft baked at a low temperature to harden the photoresist.

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Acid Etching

Etching is a common process to pattern material on the surface.

Once the desired shape is patterned with photoresist, the unprotected areas are etched away.

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Spin, Rinse, and Dry

A special tool called SRD is used to clean the wafers after each acid etch step
Use de-ionized water to

remove any residue chemical substance.


Use nitrogen because it

has no reaction with the silicon.

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Various Process Steps

The exposed area can now be subjected to a wide range of process steps
Ion implantation Plasma (Dry) etching Metal (Thin Film) deposition

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Ashing - Photoresist Removal

A high-temperature plasma is used to selectively remove the remaining photoresist without damaging previous layers. After ashing the wafer is ready for the next round of photolithography.

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Photolithographic Process Example


UV-light Si-substrate Patterned optical mask Exposed resist

Silicon base material


Si-substrate

SiO2 Si-substrate

3. Stepper exposure

1. After oxidation

heat
Photoresist SiO2 Si-substrate Si-substrate Exposed resist

2. After deposition of negative photoresist


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4. Photoresist Devolop and Bake

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Photolithographic Process Example


Chemical or plasma etch

Hardened resist SiO 2


Si-substrate Si-substrate

SiO2

5. After development and etching of resist, chemical or plasma etch of SiO2

8. Final result after removal of resist (ashing)

Hardened resist SiO2 Si-substrate

Step 7 is optional in this example. The step is need only in implanting a well or doping polysilicon Planarization step is applied at least once in a cycle of photolithography
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6. After etching and spin, rinse and dry.

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Diffusion and Ion Implantation

Change the electrical characteristics of silicon locally by adding doping agents to the exposed area. The dopant ions penetrate the surface with a penetration depth that is proportional to their kinetic energy.
1000 C

Diffusion: Wafer is exposed to


gas containing dopant under high temperature (900-1100 C)

Ion Implantation: A beam of


dopant ions is swept over the surface - causing damage to substrate, need annealing
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Purified Ion beam

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Outlines

Chip-Making Process Photolithography CMOS IC Fabrication Processes


Simple Process

Modern Process

Packaging Technology

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Photolithography Masks

Each photolithography step during fabrication must be defined by a separate photolithography mask. Each mask layer must be drawn (either manually or using a design automation tool) according to the layout design rules. The combination (superposition) of all necessary mask layers completely defines the circuit to be fabricated.
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Layout Design Rules

To allow reliable fabrication of each structure, the mask layers must conform to a set of geometric layout design rules. Usually, the rules (for example: minimum distance and/or separation between layers) are expressed as multiples of a scaling factor lambda (l) - minimum resolution of a technology

For each different fabrication technology, lambda factor can be different.


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Examples of Layout Design Rules

A Minimum-Sized Transistor
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More Example of Layout Rules

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Self-Aligned Process
1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon

3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant
(see previous slides)
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Notes on Self-Aligned Process

Polysilicon gate is patterned before source and drain are created,


Thereby defining the precise location of the channel

region and the locations of the source and drain regions relative to the gate.
And consequently reducing parasitic capacitances in

the transistor.

However, this technique cannot completely stop lateral diffusion


Accounts for difference between drawn transistor

dimensions and actual ones.


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Simplified CMOS Inverter Process


cut line

p well

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P-Well Mask

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Active Mask

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Poly Mask

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P+ Select (Source/Drain) Mask

Self-Aligned Gate

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N+ Select (Source/Drain) Mask

Self-Aligned Gate

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Contact Mask

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Metal Mask

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Outlines

Chip-Making Process Photolithography CMOS IC Fabrication Processes


Simple Process

Modern Process

Packaging Technology

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A Modern CMOS Process


Dual-Well Trench-Isolated CMOS
gate oxide field oxide Al (Cu) SiO2 tungsten

TiSi2

p well p-epi

n well

SiO2

n+

p+

Trench

p-

Both n- and p- wells grown on top of an epitaxial layer (using trench isolation areas of SiO2)
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Modern CMOS Process Walk-Through


p-epi p+

Base material: p+ substrate with p-epi layer

Si N 3 4 p-epi + p SiO 2

After deposition of gateoxide and sacrificial nitride (acts as a buffer layer)

p+

After plasma etch of insulating trenches using the inverse of the active area mask
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Modern CMOS Process Walk-Through (2)


SiO 2

After trench filling, CMP planarization, and removal of sacrificial nitride

After n-well and VTp adjust implants

After p-well and VTn adjust implants

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Modern CMOS Process Walk-Through (3)


poly(silicon)

After polysilicon deposition and etch

n +

p+

After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon.
SiO 2

After deposition of SiO2 insulator and contact hole etch

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Modern CMOS Process Walk-Through (4)


Al

After deposition and patterning of first Al layer.

Al SiO 2

After deposition of SiO2 insulator, etching of vias, deposition and patterning of second layer of Al.

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State-of-the-Art Example

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Interconnect Delay Crisis

As technology shrinks, interconnect delay has more and more impact on the overall design performance.
Wire delay now accounts for > 40% of total delay in a

circuit

There are 2 key points where interconnect delay can be reduced.


Use low-resistivity material
Copper in stead of Aluminum (what is the best conductor?)

Use insulator material with a lower dielectric

constant (k) than SiO2 (Reduce coupling)


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Advanced Metallization

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Silicon-on-Insulator (SOI)

The idea is to construct the transistor structures in a very thin layer of silicon on an insulating material rather than a common substrate as in bulk CMOS process. This reduces parasitic capacitances and eliminates substrate noise coupling.

Insulator (SiO2)

Transistor

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SOI Example

22% improvement in performance


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Fabrication Cost - Moores Law

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Initial investment of new facilities is too expensive!


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Outlines

Chip-Making Process Photolithography CMOS IC Fabrication Processes


Simple Process

Modern Process

Packaging Technology

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Packaging Technology

Many high-performance chips failed stringent test specifications after packaging because the designer (usually novice!) have not included various effects of packaging constraints and parasitics into their designs.
Ground planes, power planes, and bonding pads

greatly affect the behavior of on-chip power and ground bus.


Length of bonding wire and lead length in a package

generate a voltage drop in the output circuit.


Inappropriate type of package body can cause

thermal runaway and hence damage the ICs.


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Packaging Requirements

Electrical: Low parasitics


Low capacitance and Inductance

Mechanical: Reliable and robust


Moisture-proof High pin density

Thermal: Efficient heat removal


High thermal conductivity

Low thermal expansion coefficient

Economical: Cheap
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Bonding Techniques
Wire Bonding Wire Bonding

Substrate Die Pad

Lead Frame

High and unpredictable value of parasitics


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Tape-Automated Bonding (TAB)


Sprocket hole
Sprocket hole

Film + Pattern

Solder Bump

Test pads
Test pads Lead frame

Film + Pattern

Die Solder Bump


Die

Lead frame

Substrate (b) Die attachment using solder bumps. Substrate

Die Attachment using Polymer film Soldier bumps (b) Die attachment using solder bumps.

(a) Polymer Tape with imprinted Polymer film wiring pattern. (a) Polymer Tape with imprinted wiring pattern. Polymer Tape with imprinted

Wiring pattern
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Highly Automated, Eliminate long bonding wires


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Flip-Chip Bonding

Die Solder bumps Interconnect layers

Substrate

Alleviate power- and clock-distribution problem


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Package-to-Board Interconnect
Through-Hole Mounting Surface Mounting

(a)(a) Through-Hole Mounting Through-Hole Mounting

(b)(b) Surface Mount Surface Mount

Difficult to mount Mechanical weaker structure Higher packaging density


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Sturdy, Mechanically reliably, Lower packaging density


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Package Types
DIP - Dual-In-Line Pin

QFP - Quad Flat Pack

PGA - Pin Grid Array

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Package and Bonding Parameters

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Multi-Chip Modules

Multiple chips are assembled on a common substrate contained in a single package


A large number of critical

interconnections between the chips can be made within the package.

Advantages are savings of overall system size, reduced package lead counts, and faster operation.
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