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B.Supmonchai
Outlines
Modern Process
Packaging Technology
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Crystal Growth
Packaging
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Most common technique is the Czochralski (CZ) method developed by Mitsubishi Materials Silicon in the 50s
Length: up to 2 m
300 mm (12)
hours
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Crystal orientation is determined by seed orientation Ingot diameter is determined by temperature, orientation, and extraction speed.
CMOS Process Technology
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Wafer Shaping
Ingot is cut around and ground down into a uniform diameter (8-12), then sliced into wafers of about 1 mm thick.
The sliced wafers are mechanically lapped by the use of alumina abrasive material to remove surface roughness and damages caused by the saw cut and to improve the flatness of the wafer.
Q ui c kTi m e and a TI FF (U ncom p r essed) decompr esso r ar e n eeded to see t hi s pi ctur e.
Lapping Machine
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The mechano-chemical polishing process improves the flatness of the wafer, making highly flat surface by the use of colloidal silica.
Wafer Polishers
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VDD
PMOS
VDD 2l
PMOS
In Out
In Out
Contacts
Metal 1
NMOS
Polysilicon
Schemetic
NMOS GND
Layout
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Create contact and via windows Deposit and pattern metal layers
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liquid carrier with a suspended abrasive component such as aluminum oxide or silica
CMP (Chemical-Mechanical Planarization) - Essential to keep the surface of the wafer approximately flat between processing steps.
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Outlines
Modern Process
Packaging Technology
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Photolithography
Photolithography is used to selectively process the layers, where the 2-D mask geometry is copied on the surface.
CMOS Process Technology
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Photolithographic Process
oxide growth optical mask
stepper exposure
photoresist coating
acid etch 14
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Oxidation of the silicon surface creates a SiO2 layer that acts as an insulator. Oxide layers are also used to isolate metal interconnections.
An annealing step is required to restore the crystal structure after thermal oxidation.
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Photoresist Deposition/Coating
The surface of the wafer is coated with a photosensitive material, the photoresist. The mask pattern is developed on the photoresist, with UV light exposure.
Depending on the type of the photoresist (negative or positive), the exposed or unexposed parts of the photoresist change their property and become resistant to certain types of solvents.
CMOS Process Technology
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Stepper Exposure
A Mask Sample
Glass Mask (reticle) containing the patterns to be transferred is brought in close proximity to the wafer
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Photoresist Devolopment
The wafers are developed in either an acid or base solution to remove the nonexposed (exposed) areas of the photoresist. Once the exposed photoresist is removed, the wafer is soft baked at a low temperature to harden the photoresist.
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Acid Etching
Once the desired shape is patterned with photoresist, the unprotected areas are etched away.
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A special tool called SRD is used to clean the wafers after each acid etch step
Use de-ionized water to
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The exposed area can now be subjected to a wide range of process steps
Ion implantation Plasma (Dry) etching Metal (Thin Film) deposition
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A high-temperature plasma is used to selectively remove the remaining photoresist without damaging previous layers. After ashing the wafer is ready for the next round of photolithography.
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SiO2 Si-substrate
3. Stepper exposure
1. After oxidation
heat
Photoresist SiO2 Si-substrate Si-substrate Exposed resist
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SiO2
Step 7 is optional in this example. The step is need only in implanting a well or doping polysilicon Planarization step is applied at least once in a cycle of photolithography
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Change the electrical characteristics of silicon locally by adding doping agents to the exposed area. The dopant ions penetrate the surface with a penetration depth that is proportional to their kinetic energy.
1000 C
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Outlines
Modern Process
Packaging Technology
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Photolithography Masks
Each photolithography step during fabrication must be defined by a separate photolithography mask. Each mask layer must be drawn (either manually or using a design automation tool) according to the layout design rules. The combination (superposition) of all necessary mask layers completely defines the circuit to be fabricated.
CMOS Process Technology
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To allow reliable fabrication of each structure, the mask layers must conform to a set of geometric layout design rules. Usually, the rules (for example: minimum distance and/or separation between layers) are expressed as multiples of a scaling factor lambda (l) - minimum resolution of a technology
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A Minimum-Sized Transistor
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Self-Aligned Process
1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon
3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant
(see previous slides)
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region and the locations of the source and drain regions relative to the gate.
And consequently reducing parasitic capacitances in
the transistor.
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p well
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P-Well Mask
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Active Mask
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Poly Mask
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Self-Aligned Gate
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Self-Aligned Gate
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Contact Mask
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Metal Mask
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Outlines
Modern Process
Packaging Technology
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TiSi2
p well p-epi
n well
SiO2
n+
p+
Trench
p-
Both n- and p- wells grown on top of an epitaxial layer (using trench isolation areas of SiO2)
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Si N 3 4 p-epi + p SiO 2
p+
After plasma etch of insulating trenches using the inverse of the active area mask
CMOS Process Technology
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n +
p+
After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon.
SiO 2
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Al SiO 2
After deposition of SiO2 insulator, etching of vias, deposition and patterning of second layer of Al.
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State-of-the-Art Example
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As technology shrinks, interconnect delay has more and more impact on the overall design performance.
Wire delay now accounts for > 40% of total delay in a
circuit
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Advanced Metallization
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Silicon-on-Insulator (SOI)
The idea is to construct the transistor structures in a very thin layer of silicon on an insulating material rather than a common substrate as in bulk CMOS process. This reduces parasitic capacitances and eliminates substrate noise coupling.
Insulator (SiO2)
Transistor
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SOI Example
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Outlines
Modern Process
Packaging Technology
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Packaging Technology
Many high-performance chips failed stringent test specifications after packaging because the designer (usually novice!) have not included various effects of packaging constraints and parasitics into their designs.
Ground planes, power planes, and bonding pads
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Packaging Requirements
Economical: Cheap
CMOS Process Technology
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Bonding Techniques
Wire Bonding Wire Bonding
Lead Frame
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Film + Pattern
Solder Bump
Test pads
Test pads Lead frame
Film + Pattern
Lead frame
Die Attachment using Polymer film Soldier bumps (b) Die attachment using solder bumps.
(a) Polymer Tape with imprinted Polymer film wiring pattern. (a) Polymer Tape with imprinted wiring pattern. Polymer Tape with imprinted
Wiring pattern
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Flip-Chip Bonding
Substrate
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Package-to-Board Interconnect
Through-Hole Mounting Surface Mounting
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Package Types
DIP - Dual-In-Line Pin
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Multi-Chip Modules
Advantages are savings of overall system size, reduced package lead counts, and faster operation.
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