Low Power Area Efficient Multiplier Design

B V B CET Hubli Presented by Ranjani Vanishri

Motivation:
Low power has emerged as a principal theme in todays electronics industry.

Problem Statement:
In applications such as personal computing devices and wireless communications system, average power consumption is a critical design concern.

Objectives and specifications :

Objectives: To achieve low power less area Better performance

Specifications:
Median Filter .
The CSA multiplier is constructed using AND gates, half adder, and full adder blocks. The power dissipation and area are reduced using multiplexing method. The Multiplexing Control Input Technique (MCIT) techniques reduce the number transistor than CMOS design techniques.

Continued:
The proposed adder circuit is designed by using Shannon theorem. Pass transistor logic 1-bit multi operand addition can be extended to an n-bit multi operand addition by cascading the CSA operators.

Design analysis
Conventional AND Gate

Y=A.B
For CMOS AND gate Total no of transistor :6

Proposed AND gate:

Inputs
A 0 0 1 1 B 0 1 0 1

output
F 0 0 0 1

Total no of transistors : 4

Conventional Half Adder Design:

Total No of Transistors = 14

Proposed Half Adder

Total No of Transistors = 8

inputs
A 0 0 1 1 B 0 1 0 1

outputs
S 0 1 1 0 C 0 0 0 1

APPLICATION OF SHANNON THEOREM

C = A.B = B (A.1) + B (A.0) C = A.B + B .B

Conventional full adder

Total no of transistor :- 28

Proposed full adder

Total no of transistors : 14
S= (AB)C + (AB)C C= (AB)B + (AB)C

APPLICATION OF SHANNON THEOREM

FOR SUM CIRCUIT S= A B C S= (A B)[C 1] + ( A B)*C 0 ] S= (A B) C+ (A B)C

FOR CARRY CIRCUIT CO= A B + (A B) C CO= (A B ) (AB+1.C)+(A B) (A B+0.C) CO= (A B)B+ (A B) C

conventional BRAUN multiplier

Total no of FA :- 12 Total no of AND GATE :-16

Proposed Carry Save Array multiplier

Total no of FA:- 8 Total no of HA:- 4 Total no of AND GATE :-16

ANALYSIS
CONVENTIONAL DESIGN COMPONENT USED PROPOSED DESIGN
Area (Transistors) Area (Transistors)

AND Gate

Half Adder

18

Full Adder

14

28

ANALYSIS
COMPONENTS USED PROPOSED DESIGN (CSA multiplier) CONVENTIONAL DESIGN (BRAUN multiplier)

Area

Power(W)

Area

Power(W)

No. of AND Gates

16

20.88u

16

25.64u

Half Adders

20.69u

65.725u

Full Adders

113.52u

12

135.69u

Total Transistors required

236

7.992m

432

16.907m

RESULT
Area= 45%

Power= 52%

Future Scope
The growing market for fast floating-point coprocessors, digital signal processing chips, and graphics processors has created a demand for high speed, area-efficient multipliers. This multiplier block helps in design of low power , area and performance in the future circuits.

Conclusion
Shannon based full adder multiplier design gives better performance in terms of area and power consumption.

The proposed adder based multiplier circuits are simulated by using cadence tool.

REFERENCES
[1] S.Venkatraman, P.Karunakaran, I.Hameem Shanvas,T.Kapilachander Low Power Area Efficient Multiplier Using Shannon Based Multiplexing Logic International Journal of Embedded Systems and Applications (IJESA) Vol.2, No.2, June 2012.
[2] K.Nehru, Member, IACSIT, Dr.A.Shanmugam, S.Deepa and R.Priyadarshini A Shannon Based Low Power Adder Cell for Neural Network Training IACSIT International Journal of Engineering and Technology, Vol.2, No.3, June 2010. [3] Hajira Fathima , Jahangeer Md & Kaleem Fatima Design of Low Power Shannon Based Adder Cell using Multiplexing Control Input Technique International Conference on Electronics and Communication Engineering, April 28th-29th, 2012. [4] Anitha R1, Bagyaveereswaran V2 Brauns Multiplier Implementation using FPGA with Bypassing Techniques. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011.

THANK YOU