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BUS
Bus is the mechanism by which the CPU communicates with memory and I/O devices Bus is not just a collection of wires Bus defines the protocol for communication
Bus (2)
Shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems
Processor Control Datapath Input
Memory
Output
Bunch of Wires
Electrical Specification
Address:
Data: Control:
Complex commands
Bus Characteristics
Bus signals are usually tri-stated. Address and data lines may be multiplexed. Every device on the bus must be able to drive the maximum bus load:
Bus wires. Other bus devices.
Time Multiplexing
Share a single set of wires for multiple pieces of data Saves wires at expense of time
Master
data(15:0)
req
Servant
data(15:0)
Master
addr data
req
Servant
addr data
mux
demux
mux
demux
data(8)
addr/data
req data
15:8 7:0
req addr/data
addr data
data serializing
address/data muxing
Block transfers:
Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request
Advantages of Bus
Versatility:
New devices can be added easily
Low Cost:
A single set of wires is shared in multiple ways
Disadvantages of Bus
It creates a communication bottleneck
The bandwidth of the bus can limit the maximum I/O throughput
Parallel communication
Multiple data, control, and possibly power wires One bit per wire High data throughput with short distances Typically used when connecting devices on same IC or same circuit board Bus must be kept short long parallel wires result in high capacitance values which requires more time to charge/discharge Data misalignment between wires increases as length increases Higher cost, bulky
Serial communication
Single data wire, possibly also control and power wires Words transmitted one bit at a time Higher data throughput with long distances Less average capacitance, so more bits per unit of time Cheaper, less bulky More complex interfacing logic and communication protocol Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data increasing protocol complexity
Synchronous Bus
Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages:
Every device on the bus must run at the same clock rate To avoid clock skew, they cannot be long if they are fast
Asynchronous Bus
Asynchronous Bus:
It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol
Bus Arbitration
One of the most important issues in bus design:
How is the bus reserved by a device that wishes to use it?
Master-slave arrangement:
Only the bus master can control access to the bus:
It initiates and controls all bus requests
req data
1 2
3 4
1 2
3 4
taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
Strobe protocol
Handshake protocol
A strobe/handshake combination
Master req wait data Servant
req wait
data
req wait
1 2 3
2 taccess
1. Master asserts req to receive data 2. Servant puts data on bus within time taccess (wait line is unused) 3. Master receives data and deasserts req 4. Servant ready for next request
2. Servant can't put data within taccess, asserts wait ack 3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req 5. Servant ready for next request
Fast-response case
Slow-response case
Memory
I/O Device
C1 C4
C2
WAIT
C3
DATA
A[19-0]
ALE /MEMR CHRDY
ADDRESS
C1 C4
C2
WAIT
DATA
ADDRESS
C3
Advantage: simple
Device 2 Device N Lowest Priority Grant Release Request
wired-OR Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed
Grant
Bus Arbiter
Req
Microprocessor is executing its program. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2. Priority arbiter sees at least one Ireq input asserted, so asserts Int. Microprocessor stops executing its program and stores its state. Microprocessor asserts Inta. Priority arbiter asserts Iack1 to acknowledge Peripheral1.
Bus parking
master holds onto bus and performs multiple transactions as long as no other master makes request
7(b):
P1 de-asserts req.
R
A I/O Device
CYCLE
CLOCK
D[7-0] A[19-0] ALE /IOR /MEMW CHRDY
C1 C7
C2
C3
C4
C5
C6
CYCLE CLOCK
C1 C7
C2
C3
C4
C5
C6
DATA ADDRESS
DATA
ADDRESS
Processor-local bus
Peripheral
Peripheral
Peripheral
Bridge
Multi-level Buses
Processor-local bus
High speed, wide, most frequent communication Connects microprocessor, cache, memory controllers, etc.
Peripheral bus
Lower speed, narrower, less frequent communication Typically industry standard bus (ISA, PCI) for portability
Bridge
Single-purpose processor converts communication between busses
All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle initiator asserts cmd and address
FRAME# de-asserted when master intends to complete only one more data transfer
PC/104: Standard that specifies PC/104 size cards with both ISA and PCI
Enabling use of Pentium CPU in Embedded system A new form factor and a pass through connector
PC/104
Small Size: 3.6 x 3.8 P1 Bus has 64 pins like PC-XT P2 Bus has 40 pins
(note: 64+40=104 as in PC/104)
Provides full AT compatibility Replaces card edge connector with more reliable pin-and-socket Up to 4 modules can be stacked
SBC
SBCs follow the technology developed by the PC Industry Basic Architecture ISA/PCI Bus protocol Serial & Parallel Port The latest SBCs provide all the flexibility and power of a PC with very small space requirements PC/104 and PC/104 plus meet the need of SBCs
Summary
We have studied about Bus connecting CPU to memory and I/O devices There may be more than one bus master
We need arbitration
We shall look at the nature of buses used in SOCs We shall also study serial buses
BUS STRUCTURE-2
SOC BUS SERIAL BUS
Recap: SBC
SBCs follow the technology developed by the PC Industry
Basic Architecture ISA/PCI Bus protocol Serial & Parallel Port
The latest SBCs provide all the flexibility and power of a PC with very small space requirements
Software Compatibility
Bridge
A bridge is a slave on the fast bus and master of the slow bus Takes command from the fast bus on which it is slave Issues commands on the slow bus Returns results from slow bus to fast bus Also functions as protocol translator
The System-on-a-Chip
System Bus
DMA CPU DSP
MPEG
I C
System-on-a-chip (SoCs) requires busing systems to connect various components, including one or more microprocessors, memory, peripherals, and special logic
AMBA standardizes the bus interface Allows increased re-use of IP in designs Enable the creation of upgrades and families of devices
Arbiter
AMBA
ARM
Bus Interface On-chip RAM
Reset
Remap/ Pause
Decoder
Interrupt Controller
AMBA
AMBA is a multi-level Bus ASB/AHB: Advanced System Bus: To connect High Performance modules APB: Advanced Peripheral Bus: Simpler interface for low performance peripherals Support 32-, 64-, and 128-bit data-bus implementations with a 32-bit address bus
as well as smaller byte and half-word designs.
AHB
The AHB puts the address on the bus, followed by the data. It supports wait-state insertion and has a data-valid signal (HREADY). It has separate read (HRDATA) and write (HWDATA) buses.
AHB operation
AHB supports bursts, with 4-, 8-, and 16-beat bursts, as well as undefinedlength bursts and single transfers.
Bursts can be address wrapped, i.e., staying within a fixed address range. Slaves can insert wait states to adjust its response (up to 16).
Bus operation
All bus operations are initiated by bus masters, which also can serve as a slave. The master-generated address is decoded by a central address decoder that provides a select signal to the addressed bus slave unit. The bus master can "lock" the bus, reserving it with the central arbiter for a series of locked transfers.
Arbitration
Master x requests for the AHB by issuing req[x] When bus is available the arbiter issues a hgrant[x] to master x Upon receiving grant signal master issues address and control information to indicate the type of transfer
master 1
slave 1
master 2
slave 2
master 3
slave 3
Bus transaction
The slave unit has the option to terminate a transaction
as an error, signal the master to retry, or split the transaction for later completion.
Split transactions enable the slave to defer the operation until it's able to accomplish it,
thereby releasing the bus for other accesses.
Split Transaction
The slave signals a split transaction and saves the master number (HMASTER[]). When ready to complete the transaction, the slave signals the arbiter with the master number. When the arbiter grants bus access to the master, it restarts the transaction.
No master can have more then 1 pending split transaction.
AHB Signals
The signals are driven by the active bus master and have the same timing as the address bus.
HTRANS[1:0]
Transfer signals indicate the type of the next transaction, which may be address-only, nonsequential or sequential. These signals are driven by a bus master when the appropriate GRANTx signal asserted.
Timing Diagram
APB
Designed to support low-speed peripherals such as UARTs, keypads, and PIO All bus devices are slaves to the master, the bridge to the AHB, or ASB system bus. Provides a simple address, with latched address and control signals for easy interfacing. APB can be implemented with a single tristated data bus.
APB Bridge
APB Transaction
As a simple bus, the APB doesn't support bursting. Each transaction consists of 2 cycles: an address cycle (Setup state) and a data cycle (Enable state). The bus uses a single clock, PCLK.
In Setup, the bus brings PSEL and PWRITE up, putting the address on the PADDR address bus. In the Enable state, it brings PENABLE up and places data on the PWDATA/PRDATA bus. The enable signal, PENABLE, is de-asserted on the next clock.
System Architecture
Connecting IP cores and on-chip communication interface Synthesis/Timing Analysis Friendly Encompass entire core/system interface needs (data, control, and test flows)
IP Core
Master Slave
IP Core
Slave Request Response
Slave
Master
Target
Master
On-Chip Bus
Protocol Phases
Request Phase (begins Transfer)
Master presents request (command, address, etc.) to Slave
Protocol Phases
Datahandshake Phase (Optional)
Allows pipelining request ahead of write data Only available for write transfers
Phase ordering
Request -> Datahandshake -> Response
Use of Protocol
A designer selects only those signals and features from the palette of OCP configurations needed to fulfill all of an IP cores unique data, control and test signaling requirements
Serial Buses
Serial Protocol
Used for moving data quickly from one device to another Serial protocols like I2C & SPI are meant for short distances inside the box
Low complexity Low cost
I2C
Meant for inter-Integrated Circuit Communication Developed by Philips Semiconductor for TV sets in the 1980s I2C devices include EEPROMs, thermal sensors, and real-time clocks Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors.
I2C: Features
Bi-directional
Data can flow in both directions
Synchronous
Data is clocked along with a clock signal Clock signal controls when data is changed and when it should be read Clock rate can vary unlike asynchronous (RS-232 style) communication I2C bus has three speeds: Slow (under 100 Kbps) Fast (400 Kbps) High-speed (3.4 Mbps) I2C v.2.0
I2C: Connections
Two wired bus
Serial data line(SDA) Serial Clock line (SCL)
Voltage Levels
High - 1 Low - 0
Bit transfer
SCL=1 implies SDA = valid data Stable data during high clock Data change during low clocks
Basic Protocol
I2C is a master slave protocol
Master device controls the clock (SCL) Slave devices may hold the clock low to prevent data transfer No data is transferred unless a clock signal is present All slaves are controlled by the master clock
Summary
We have studied bus specifications used in a SOC Looked at a serial bus for connecting devices to a micro-controller We shall learn more about serial buses in the next class
Bus Structure-3
Serial Interfaces
I2C: Basics
Two wired bus
Serial data line(SDA) Serial Clock line (SCL)
Voltage Levels
High - 1 Low - 0
Bit transfer
SCL=1 implies SDA = valid data Stable data during high clock Data change during low clocks
I2C Signals
I2C lines can have two possible states
Float high Drive low
Pull-up resistor on the line and only devices pull the line low
If no device is pulling on the line it will float high
Wired-and Connection
Bus is free implying SDA and SCL are high
By pull-up resistors
Frame
Start Condition(S)
SDA 1->0 transition when SCL=1
Stop Condition(P)
SDA 0->1 transition when SCL=1
Bus state
Busy - after S and before next P Free after P and before next S
Data transfer
Data bits are transferred after start condition Transmission is byte oriented
8 bits + 1 acknowledge bit
Addressing Scheme
First byte transmitted by master
7 bits: address 1 bit: direction(R/W)
0 master writes data 1 master receives data
Master may generate repeated start and address another device Each device listens to address
If address matches device switches state according to R/W bit
After ack
Master tries to generate next bytes first pulse Slave can hold SCL low forcing master to switch to wait state
Frame Format
Bus Arbitration
I2C designed as a multi-master bus
Any one of several different devices may act as the master at various times No global master to generate clock
A master drives both SCL and SDL
I2C in PIC
In PIC micro-controller MSSP module provides the support for I2C
MSSP
I2C in PIC
I2C Tradeoffs
Advantages:
Good for communication with on-board devices that are accessed occasionally. Easy to link multiple devices because of addressing scheme Cost and complexity do not scale up with the number of devices
Disadvantages:
The complexity of supporting software components can be higher than that of competing schemes ( for example, SPI ).
SPI
Shorthand for Serial Peripheral Interface Defined by Motorola on the MC68HCxx line of microcontrollers
Generally faster than I2C, capable of several Mbps
Applications:
Like I2C, used in EEPROM, Flash, and real time clocks Better suited for data streams, i.e. ADC converters Full duplex capability, i.e. communication between a codec and digital signal processor
Master
Slave
Bus Signals
Synchronous serial data link operating at full duplex Master/slave relationship 2 data signals:
MOSI master data output, slave data input
Also called SDO : serial data output
2 control signals:
SCLK clock /SS slave select (no addressing)
For multiple slaves, each slave needs separate slave select signal
More effort and more hardware than I2C
SPI Protocol
2 Parameters, Clock Polarity (CPOL) and Clock Phase (CPHA), determine the active edge and idle state of the clock
CPOL 0 0 1 1 CPHA 0 1 0 1 Active edge Rising Falling Falling Rising
Master and slave must agree on parameter pair values in order to communicate
SPI in PIC
The SSP and MSSP module in PIC can implement SPI protocol
I2C by MSSP only
Serial buffer: Data is put after SPI transfer or before SPI transfer
USB
USB is a serial protocol and physical link
transmits all data differentially on a single pair of wires. Another pair provides power to downstream peripherals
USB signaling
Speeds:
High-speed is 480 Mb/s. Full-speed is 12 Mb/s. Low-speed is 1.5 Mb/s.
Signals:
Vbus, Gnd. D+, D-.
USB power
USB devices can pull a limited amount of power from the bus.
May also supply their own power.
USB architecture
USB Peripherals are slaves responding to commands from the host. When a peripheral is attached to the USB network, the host communicates with the device
To learn its identity and To discover which device driver is required (a process called enumeration ).
USB devices
The specification recognizes two kinds of peripherals:
Stand-alone (single function units, like a mouse) Compound devices (those that have more than one peripheral sharing a USB port).
An example of a compound device is a video camera with separate audio processor.
Summary
We have studied serial interfaces for connecting peripherals We have also looked at serial bus protocol for connecting embedded systems to hosts
Serial Intefaces
USB, IEEE 1394, IrDA
Bus Protocol
data transfer
token
Host controller initiates data transfer by generating token packet Data transferred Handshake packet for completion
port
Hub
port
port
device
USB Organization
USB Hubs
Hubs are bridges
Increase the logical and physical fan-out of the network.
A hub has a single upstream connection Many downstream connections.
Hubs are themselves USB devices Hubs detect topology changes due insertion/deletion of devices. They also source power to the USB network
USB Communication
Communications between the host and endpoints located in the peripherals.
An endpoint is a uniquely addressable portion of the peripheral that is the source or receiver of data. Four bits define the device's endpoint address; Codes also indicate transfer direction and the transaction
PIPE
Pipe: all transfers occur through virtual pipes that connect the peripheral's endpoints with the host. When establishing communications with the peripheral, each endpoint returns a descriptor
Descriptor is a data structure that tells the host about the endpoint's configuration and expectations.
Include transfer type, max size of data packets, perhaps the interval for data transfers, and in some cases, the bandwidth needed.
Control transfers exchange configuration, setup, and command information between the device and the host.
Interrupt transfer
Interrupt transfers, though not interrupts in the CPU-diverting sense, poll devices to see if they need service.
Peripherals exchanging small amounts of data that need immediate attention (such as mice and keyboards) use interrupt transfers. Error checking validates the data.
Isochronous transfer
Isochronous data transfer ensures that data flows at a pre-set rate so that an application can handle it in a timed way. Isochronous transfers handle streaming data like that from an audio or video device. It is time sensitive information so, within limitations, it has guaranteed access to the USB bus. No error checking occurs so the system must tolerate occasional scrambled bytes.
IEEE 1394
Firewire:features
Packet-based layered design structure Applications using FireWire include:
disk drives, printers, scanners, cameras
Connecting Devices
In work area #1 a video camera, PC, and video recorder, all interconnected PC is also connected to a physically distant printer via a 1394 repeater
Repeater extends the interdevice distance by redriving the 1394 signals.
A 1394 splitter is used to provide another port to attach a 1394 bus bridge.
Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm
Connecting Devices
The 1394 bus bridge isolates data traffic within each work area. Bus bridges allow selected data to be passed from one bus segment to another.
PC #2 can request image data from the video recorder in work area #1. Since the 1394 cable is powered, the signalling interface is always powered Video data is transported even if PC #1 is powered off.
Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm
Protocol Stack
Soure: Xilinx
Physical Layer
Physical layer provides the initialization and arbitration services
It assures that only one node at a time is sending data
Includes
Electrical signaling Mechanical connectors and cabling Arbitration mechanism Serial coding and decoding of data being transferred or received Transfer speed detection
Link Layer
Extracts and put data packets on and off the wire Does error detection and correction Does retransmission Handles provision for cycle control for isochronous channel Link layer supplies an acknowledged datagram to the transaction layer
A datagram is a one-way data transfer with request confirmation
Transaction Layer
Implements Request-response protocol Minimizes amount of circuitry required to interconnect with standard buses such as the PCI bus
Host Controller
Soure: Xilinx
Wireless Protocol
IRDA
Wireless communication
Infrared (IR)
Electronic wave frequencies just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal, conducts when exposed to infrared light Cheap to build Need line of sight, limited range
IrDA
IrDA is a standard defined by the IrDA consortium (Infrared Data Association). Specifies a way to wirelessly transfer data via infrared radiation. Specifications include standards for both the physical devices and the protocols they use to communicate with each other. Can connect various mobile/embedded systems
Primary use has been to link notebooks or various personal communicators
Features
Most IrDA work over distances up to 1.0m with BER 10-9 and maximum level of surrounding illumination 10klux (daylight).
Bit Error Ratio - number of incorrectly transferred bits over number of correctly transferred bits
Pulse modulation with 3/16 of the length of the original duration of a bit is used. Data format is the same as for a serial port asynchronously transmitted word, with a start bit at the beginning.
Pulse width
Transmitter can use either 3/16 mark-tospace ratio for one bit, or a fixed length 1.63 us of each optical pulse, which would correspond to 115kbps (ver1.0).
IR Frame
IR-LED's can not transmit at full power continuously over 100% of time. So, a pulse width of only 3/16 of the total time for one bit is used.
Integrated IrDA transceivers do have filters that eliminate noise other than the IrDA frequency range 2400-115200 bps
Packet Structure
A packet consists of two start words followed by target address
IrDA devices are assigned numbers by the means of IrDA protocol, so they are able to unambiguously identify themselves
Followed by data, CRC-16 and a stop word. The whole packet (frame) including CRC-16 is generated by IrDA compatible chipset. Start and stop words last 1.5times the bit duration (6 times longer flash than usual).
Protocols
IrDA Infrared Link Access Protocol (IrLAP)
Encapsulates the frames Provides arbitration
Only one primary device, others are secondary The communication is always half-duplex
Describes how the devices establish connection, close it, and how are they going to be internally numbered.
IrDA Protocols
IrDA Infrared Link Management Protocol (IrLMP)
Every device lets the others know about itself via the IrLMP protocol, which runs above IrLAP IrLMP's goal is to detect presence of devices offering a service, to check data flow, and to act as a multiplexer for configurations with more devices with different capabilities involved Applications use the IrLMP layer to ask if a required device is within range, etc.
Protocols
IrDA Transport Protocols (Tiny TP)
This layer manages virtual channels between devices, performs error corrections (lost packets, etc.), divides data into packets, and reassembles original data from packets.
Application Protocols
Extensions to IrOBEX for Ir Mobile Communications
Extension for mobile devices - handhelds, PDA, cellular phones - defines how to transfer informations pertaining to GSM network
address books, SMS, calendar, dialing control, digital voice transfer over IR, etc.
Application of IrDA
Wireless Communication
Radio frequency (RF)
Electromagnetic wave frequencies in radio spectrum Analog circuitry and antenna needed on both sides of transmission Line of sight not needed, transmitter power determines range
Generic Issues
Serial high speed buses for connecting processor to memory and peripherals Use of packet switching for improving transfer efficiency
Split transaction
Example: PCI-express
Summary
We have studied about bus structures used for connecting CPU and peripherals We have also looked at the interface specifications for connecting two or more systems