DIPLOMA IN VLSI DESIGN

VHDL CONSTRUCTS - I

Clock Skew Definitions: The difference between arrival times of the clock at different devices is called clock skew.

Example of clock skew:

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DIPLOMA IN VLSI DESIGN

VHDL CONSTRUCTS - I

Clock Skew
Buffering the clock: In a large system, the single clock signal may not have adequate fanout to drive all of the devices, so it may be necessary to provide one or two copies of the clock signal.

The buffering method of figure (a) produces excessive clock skew, since CLOCK1 and CLOCK2 are delayed through an extra buffer compared to CLOCK. A recommended method is shown in figure (b). All of the clock signals go through identical buffers, and thus have roughly equal delays.

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VHDL CONSTRUCTS - I

Minimizing the clock skew

Add Delay in Data Path:

The amount of the inserted delay (number of BUFD or INVD macros) in the data path should be large enough so that the delay becomes sufficiently greater than the clock skew.

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VHDL CONSTRUCTS - I

Minimizing the clock skew

Clock Reversing:

In this method, the clock signal arrives at the clock port of the destination register sooner than the source register. Therefore, the destination register will clock in the source register (current) value before the source register receives its clock edge. The clock reversing method will not be effective in circular structures such as Johnson counters because it is not possible to define the source register explicitly.

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Minimizing the clock skew

Clock Reversing in circular structure:

In this example, the clock skew problem exists between flip-flops U1 and U3.

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Minimizing the clock skew

Alternate Phase Clocking: The following are the most common methods of alternate phase clocking: 1. Clocking on alternate edges 2. Clocking with two phases 1. Clocking on alternate edges:

In this method, the sequentially adjacent registers are clocked on opposite edges of the clock. This method provides a short path-clock skew margin of about one-half clock cycle.

2004 Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL CONSTRUCTS - I

Minimizing the clock skew

Signal propagation for previous circuit:

2004 Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL CONSTRUCTS - I

Minimizing the clock skew

Clocking with two phases:

In this method, the sequentially adjacent registers are alternatively clocked on two different phases of the same clock. In this case, between each two adjacent registers, there is a safety margin approximately equal to the phase difference of the two phases.

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VHDL CONSTRUCTS - I

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2004 Centre for Development of Advanced Computing