Finite State Machine Implementation

Outline Implementation Strategies discrete logic design with counters, ROMs programmable logic PALs FGPAs: Altera, Actel, Xilinx

Implementation Strategies Discrete Gate Logic Emphasis so far MSI Logic (e.g., Counters) Structured Logic (e.g., PLA/PAL, ROM) Field Programmable Gate Arrays (FPGAs) Function can be configured "on the fly" or in the field Flipflops/Registers plus discrete gates on the same chip

Implementation Strategies FSM Design with Structured Logic

Combinational Logic Inputs Output Function Next State Function

Registers Outputs

Block Diagram for Synchronous Mealy Machine

State

ROM-based Realization
ROM A0 Inputs An-1 An Dk-1 Dk D0 Outputs Registers

Inputs & Current State form the address ROM data bits form the Outputs & Next State

An+m-1 Dk+m-1

State

Implementation Strategies ROM-based Design Example: BCD to Excess 3 Serial Converter BCD Excess 3 Code 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1000 0110 1001 0111 1010 1000 1011 1001 1100

Conversion Process Bits are presented in bit serial fashion starting with the least significant bit

Single input X, single output Z

Implementation Strategies BCD to Excess-3 Converter

Next X=0 S1 S3 S4 S5 S5 S0 S0 State X=1 S2 S4 S4 S5 S6 S0 -Output X=0 X=1 1 0 1 0 0 1 0 1 1 0 0 1 1 -Reset S0

Present State S0 S1 S2 S3 S4 S5 S6

State Transition Table

0/1 S1 0/1 1/0

1/0 S2 0/0, 1/1

Derived State Diagram

S3 0/0, 1/1 S5 0/0, 1/1 0/1

S4 1/0

S6 0/1

Implementation Strategies BCD to Excess 3 Converter ROM-based Implementation

ROM Address X Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 ROM Outputs Z D2 D1 D0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 0 X X X X 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 0 0 0 X X X X X X X X

1 CLK 1 0 X conv erter ROM Z X D2 Q2 D1 Q1 D0 Q0 1 0 9 13 12 5 4 CLK D C B A QD 175 QD QC QC QB QB 15 14 10 11 7 6 Z

1 CLR \Reset

2 QA 3 QA

Circuit Level Realization 74175 = 4 x positive edge triggered D FFs

Truth Table/ROM I/Os

In ROM-based designs, no need to consider state assignment

Implementation Strategies BCD to Excess-3 Converter LSB MSB Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)

X Z CLK \Reset

0 1

0 1

0 0

0 0

1 0

1 1

1 0

0 1

0000 LSB

1100

1110 LSB

0101

Implementation Strategies BCD to Excess 3 Converter PLA-based Design State Assignment with NOVA

0 1 0 1 0 1 0 1 0 1 0 1 0

S0 S0 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6

S1 S2 S3 S4 S4 S4 S5 S5 S5 S6 S0 S0 S0

1 0 1 0 0 1 0 1 1 0 0 1 1

S0 = 000 S1 = 001 S2 = 011 S3 = 110 S4 = 100 S5 = 111 S6 = 101 NOVA derived state assignment 9 product term implementation

NOVA input file

Implementation Strategies

BCD to Excess 3 Converter

.i 4 .o 4 .ilb x q2 .ob d2 d1 .p 16 0 000 001 1 000 011 0 001 110 1 001 100 0 011 100 1 011 100 0 110 111 1 110 111 0 100 111 1 100 101 0 111 000 1 111 000 0 101 000 1 101 --0 010 --1 010 --.e Espresso Inputs q1 q0 d0 z 1 0 1 0 0 1 0 1 1 0 0 1 1 -

Espresso Outputs

.i 4 .o 4 .ilb x q2 q1 q0 .ob d2 d1 d0 z .p 9 0001 0100 10-0 0100 01-0 0100 1-1- 0001 -0-1 1000 0-0- 0001 -1-0 1000 --10 0100 ---0 0010 .e

Implementation Strategies

BCD to Excess 3 Converter

D2 = Q2 Q0 + Q2 Q0 D1 = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0 D0 = Q0 Z = X Q1 + X Q1
1 CLK 9 1 0 X conv erter PLA X Q2 Q1 Q0 Z D2 D1 D0 1 0 13 12 5 4 CLK D C B A 15 QD 14 QD 10 QC 11 QC 7 QB 6 QB 2 QA 3 QA

175

1 CLR \Reset

Implementation Strategies BCD to Excess 3 Serial Converter 10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate D1 = D11 + D12 D11 = X Q2 Q1 Q0 + X Q2 Q0 D12 = X Q2 Q0 + Q1 Q0
0 1 2 3 X 0 1 D2 45 89 12 13 16 17 20 21 24 25 28 29 30 31

0. Q2 Q0 1. Q2 Q0 8. X Q2 Q1 Q0 9. X Q2 Q0 16. X Q2 Q0 17. Q1 Q0 24. D11 25. D12 32. Q0 33. not used 40. X Q1 41. X Q1

Q2 8 9 Q1 16 17 Q0 24 25 D11 32 33 D12 40 41 Z D0 D1 D12 D11

Implementation Strategies BCD to Excess 3 Serial Converter

0 1 2 3 X 0 1 Q2 8 9 Q1 16 17 Q0 24 25 D11 32 33 D12 40 41

45

89

12 13 16 17 20 21 24 25

28 29 30 31

D2

D11

D12

D1

D0

Implementation Strategies More Advanced PAL Architectures

Registered PAL Architecture

Buffered Input or product term

CLK Q2 Q0 + Q2 Q0 OE

Q2 Q0 Q2 Q0

D2 DQ Q

Q2+

Q2+

Q2+ X Q2 Q0 + Q2 Q0

Q2 Q2

Q0 Q0

D2 = Q2 Q0 + Q2 Q0

Negative Logic Feedback

D1 = X Q2 Q1 Q0 + X Q2 + X Q0 + Q2 Q0 + Q1 Q0 D0 = Q0 Z = X Q1 + X Q1

Implementation Strategies Advanced PAL Architectures Programmable Output Polarity/XOR PALs

CLK OE

DQ Q

Buried Registers: decouple FF from the output pin

Advantage of XOR PALs: Parity and Arithmetic Operations

AB AB AB AB AB AB AB AB C C C C C C C C D D D D D D D D A B C D AB AB CD CD A B C D

Implementation Strategies Example of XOR PAL

INCREMEN T 1 0 FIRST FUSE NUMBER 0 40 80 120 Q 2
2

Example of Registered PAL

INCREMEN T 1 0 4 8 12 16 20 24 28

12

16

20

24

28

32

36 D Q 23
FIRST FUSE NUMBER S

0 32 64 96 128 160 192 224

19

160 200 240 280

Q Q

22

3 320 360 400 440

256 288 320 352 384 416 448 480 3 512 544 576 608 640 672 704 736 4

Q Q

18

Q Q

21

4 480 520 560 600

Q Q

17

Q Q

20

5 640 680 720 760

Q Q

19

768 800 832 864 896 928 960 992 5

Q Q

16

6 800 840 880 920

1024 1056 1088 1120 1152 1184 1216 1248 6

Q Q

18

Q Q

15

7 960 1000 1040 1080 Q 8 1120 1160 1200 1240 Q 9 1280 1320 1360 1400 Q 10 1440 1480 1520 1560 Q 11 INCREMEN T 0 4 8 12 16 20 24 28 32 36 13
9

17

1280 1312 1344 1376 1408 1440 1472 1504 7 1536 1568 1600 1632 1664 1696 1728 1760 8 1792 1824 1856 1888 1920 1952 1984 2016

Q Q

14

16

Q Q

13

15

12

14

11

NOTE: FUSE NUMBER = FIRST FUSE NUMBER + INCREMENT

Implementation Strategies Specifying PALs with ABEL

P10H8 PAL

module bcd2excess3 title 'BCD to Excess 3 Code Converter State Machine' u1 device 'p10h8';
"Input Pins X,Q2,Q1,Q0,D11i,D12i "Output Pins D2,D11o,D12o,D1,D0,Z pin pin 1,2,3,4,5,6; 19,18,17,16,15,14;

INSTATE = [Q2, Q1, Q0]; S0 = [0, 0, 0]; S1 = [0, 0, 1]; S2 = [0, 1, 1]; S3 = [1, 1, 0]; S4 = [1, 0, 0]; S5 = [1, 1, 1]; S6 = [1, 0, 1]; equations D2 = (!Q2 & Q0) # (Q2 & !Q0); D1 = D11i # D12i; D11o = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0); D12o = (!X & Q2 & !Q0) # (Q1 & !Q0); D0 = !Q0; Z = (X & Q1) # (!X & !Q1); end bcd2excess3;

Explicit equations for partitioned output functions

Implementation Strategies Specifying PALs with ABEL

P12H6 PAL

module bcd2excess3 title 'BCD to Excess 3 Code Converter State Machine' u1 device 'p12h6';
"Input Pins X, Q2, Q1, Q0 "Output Pins D2, D1, D0, Z pin pin 1, 2, 3, 4; 17, 18, 16, 15; Q0]; OUTSTATE = [D2, D1, D0]; S0out = [0, 0, 0]; S1out = [0, 0, 1]; S2out = [0, 1, 1]; S3out = [1, 1, 0]; S4out = [1, 0, 0]; S5out = [1, 1, 1]; S6out = [1, 0, 1];

INSTATE = [Q2, Q1, S0in = [0, 0, 0]; S1in = [0, 0, 1]; S2in = [0, 1, 1]; S3in = [1, 1, 0]; S4in = [1, 0, 0]; S5in = [1, 1, 1]; S6in = [1, 0, 1];

Simpler equations

equations D2 = (!Q2 & Q0) # (Q2 & !Q0); D1 = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0) # (!X & Q2 & !Q0) # (Q1 & !Q0); D0 = !Q0; Z = (X & Q1) # (!X & !Q1); end bcd2excess3;

Implementation Strategies Specifying PALs with ABEL

P16R4 PAL
module bcd2excess3 title 'BCD to Excess 3 Code Converter' u1 device 'p16r4'; "Input Pins Clk, Reset, X, state_diagram SREG state S0: if Reset then S0 else if X then S2 with Z = 0 else S1 with Z = 1 state S1: if Reset then S0 !OE pin 1, 2, 3, 11; else if X then S4 with Z = 0 else S3 with Z = 1 state S2: if Reset then S0 pin 14, 15, 16, 13; else if X then S4 with Z = 1 else S4 with Z = 0 D0]; state S3: if Reset then S0 else if X then S5 with Z = 1 else S5 with Z = 0 state S4: if Reset then S0 else if X then S6 with Z = 0 else S5 with Z = 1 state S5: if Reset then S0 else if X then S0 with Z = 1 else S0 with Z = 0 state S6: if Reset then S0 else if !X then S0 with Z = 1

"Output Pins D2, D1, D0, Z

SREG S0 = S1 = S2 = S3 = S4 = S5 = S6 = = [D2, [0, 0, [0, 0, [0, 1, [1, 1, [1, 0, [1, 1, [1, 0, D1, 0]; 1]; 1]; 0]; 0]; 1]; 1];

end bcd2excess3;

Implementation Strategies FSM Design with Counters Synchronous Counters: CLR, LD, CNT

Four kinds of transitions for each state: (1) to State 0 (CLR)

0 no signals asserted LD m

CLR
(2) to next state in sequence (CNT) (3) to arbitrary next state (LD) (4) loop in current state

CNT n+1

Careful state assignment is needed to reflect basic sequencing of the counter

Implementation Strategies

FSM Design with Counters Excess 3 Converter Revisited

Reset 0/1 1 0/1 1/0 0 1/0 4 0/0, 1/1 5 0/1 1/0 6 0/1
Note the sequential nature of the state assignments

2 0/0, 1/1 3 0/0, 1/1

Implementation Strategies FSM Design with Counters Excess 3 Converter

Inputs/Current Next State State X Q2 Q1 Q0 Q2+ Q1+ Q0+ 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 X X X 1 0 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 X X X 1 1 1 1 X X X Outputs

Z CLR LD 1 1 1 1 1 1 0 1 1 0 0 X 1 1 1 0 1 0 1 0 X X X X 0 1 0 0 1 0 1 1 1 1 0 X 0 1 1 1 1 1 X X X X X X

EN 1 1 1 X 1 X X X X X 1 X 1 1 X X

C X X X X X 0 X X 1 1 X X X X X X

B X X X X X 1 X X 0 0 X X X X X X

A X X X X X 1 X X 0 1 X X X X X X

CLR signal dominates LD which dominates Count

Implementation Strategies

Implementing FSMs with Counters

Excess 3 Converter .i 5 .i 5 Espresso Input File .o 7 .o 7 .ilb res x q2 q1 q0 .ilb res x q2 q1 q0 .ob z clr ld en c b a .ob z clr ld en c b a .p 17 .p 10 1---- -0----0-001 0101101 00000 1111---0-01 1000000 00001 1111---11-0 1000000 00010 0111--0-0-0 0101100 00011 00-----000- 1010000 00100 0111---0--0 0010000 00101 110-011 0-10- 0101011 00110 10------11- 1000000 00111 -------11-- 0010000 01000 010-100 -1-1- 1010000 01001 010-101 .e 01010 1111--Espresso Output File 01011 10----01100 1111--01101 0111--01110 ------01111 ------.e

Implementation Strategies FSM Implementation with Counters Excess 3 Converter Schematic

CL K 1 0 1 0 exce ss 3 PL A X Re set X Q2 Q1 Q0 Z \CLR \LD EN C B A 7 P 10 163 T RCO 15 2 CL K 6 D QD 11 5 C QC 12 4 B QB 13 3 A 14 QA 9 LOA D 1 CL R D Q C Q Z

Synchronous Output Register

Implementation Strategies FSM Design with More Sophisticated PLDs

Programmable Logic Devices = PLD

PALs, PLAs = 10 - 100 Gate Equivalents

Field Programmable Gate Arrays = FPGAs Altera MAX Family Actel Programmable Gate Array

Xilinx Logical Cell Array

100 - 1000(s) of Gate Equivalents!

Implementation Strategies Design with More Sophisticated PLDs Altera EPLD (Erasable Programmable Logic Devices) Historical Perspective: PALs - same technology as programmed once bipolar PROM EPLDs - CMOS erasable programmable ROM (EPROM) erased by UV light Altera building block = MACROCELL
CLK Clk MUX

8 Product Term AND-OR Array + Programmable MUX's

AND ARRAY Inv ert Control

Output MUX

pad

I/O Pin

F/B MUX

Seq. Logic Block

Programmable polarity

Programmable feedback

Implementation Strategies Design with More Sophisticated PLDs Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits:
Global CLK 1 OE/Local CLK Q EPROM Cell Global CLK 1 OE/Local CLK Q EPROM Cell Clk MUX

Synchronous Mode

Flipflop controlled by global clock signal

local signal computes output enable

Clk MUX

Asynchronous Mode

Flipflop controlled by locally generated clock signal

+ Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function

Implementation Strategies Design with More Sophisticated PLDs AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Altera solution: Multiple Array Matrix (MAX)

Logic Array Blocks (similar to macrocells)

LAB A

LAB H

Global Routing: Programmable Interconnect Array EPM5128: 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB

LAB B

LAB G

LAB C

P I A
LAB F

LAB D

LAB E

Implementation Strategies Design with More Sophisticated PLDs LAB Architecture

I/O Pad Macrocell ARRAY I N P U T S I/O Block

. . .
I/O Pad

P I A Expander Product Term ARRAY

Macrocell P-Terms

Expander P-Terms

Expander Terms shared among all macrocells within the LAB

Implementation Strategies P22V10 PAL

INCREMENT 1 0 0 FIRST FUSE NUMBERS 44 88 132 176 220 264 308 352 396
1 1 AR D Q Q SP P R 1 0 5809 1 0 0 0 0 1 5808

2904 4 8 12 16 20 24 28 32 36 40
ASYNCHRONOUS RESET (TO ALL REGISTERS)

23

2948 2992 3036 3080 3124 3168 3212 3256 3300 3344 3388 3432 3476 3520 3564 3608 6

OUTPUT LOGIC MACROCEL L

18

P - 5818 R - 5819

440 3652 484 528 572 616 660 704 748 792 836 880 2 924 968 1012 1056 1100 1144 1188 1232 1276 1320 1364 1408 1452 3 1496 1540 1584 1628 1672 1716 1760 1804 1848 1892 1936 1980 2024 2068 2112 4 2156 2200 2244 2288 2332 2376 2420 2464 2508 2552 2596 2640 2684 2728 2772 2816 2860 5 7 4312
OUTPUT LOGIC MACROCELL

OUTPUT LOGIC MACROCELL

22

P - 5810 R - 5811

3696 3740 3784 3828 3872 3916 3960 4004 4048 4092 4136 4180 4224 4268

OUTPUT LOGIC MACROCEL L

17

P - 5820 R - 5821

21

P - 5812 R - 5813

4356 4400 4444 4488 4532 4576 4620 4664 4708 4752 4796 4840 8 4884 4928 4972 5016 5060 5104 5148 5192 5236 5280 5324 9 5368 5412 5456 5500 5544 5588 5632 5676 5720

OUTPUT LOGIC MACROCEL L

16

P - 5822 R - 5823

OUTPUT LOGIC MACROCELL

20

OUTPUT LOGIC MACROCEL L

15

P - 5814 R - 5815

P - 5824 R - 5825

OUTPUT LOGIC MACROCEL L

14

OUTPUT LOGIC MACROCELL

19 10

P - 5826 R - 5827

P - 5816 R - 5817

5764 11 INCREMEN T 0 4 8 12 16 20 24 28 32 36 40

SYNCHRONOUS PRESET (TO ALL REGISTERS)

13

Supports large number of product terms per output Latches and muxes associated with output pins

Implementation Strategies Design with More Sophisticated PLDs Actel Programmable Gate Arrays
I/O Buffers, Programming and Test Logic

Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once

I/O Buffers, Programming and Test Logic

I/O Buffers, Programming and Test Logic

---

---

---

---

---

---

Use Anti-fuses to build up long wiring runs from short segments

I/O Buffers, Programming and Test Logic Logic Module

Wiring Tracks

8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates

Implementation Strategies Actel Logic Module

SOA S0 S1

Basic Module is a Modified 4:1 Multiplexer

D0 2:1 MUX D1 2:1 MUX D2 2:1 MUX D3 Y

SOB

"0"

Example: Implementation of S-R Latch

2:1 MUX "0" 2:1 MUX "1" 2:1 MUX Q

Implementation Strategies Actel Interconnect

Logic Module

Horizontal Track

Anti-fuse

Vertical Track

Interconnection Fabric

Implementation Strategies Actel Routing Example

Logic Module

Input Logic Module Output Logic Module

Input

Jogs cross an anti-fuse minimize the # of jogs for speed critical circuits 2 - 3 hops for most interconnections

Implementation Strategies Design with More Sophisticated PLDs Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 1's and 0's on power up
IOB IOB IOB IOB

IOB

General Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring Channels

IOB

CLB

CLB

Wiring Channels

IOB

CLB

CLB

IOB

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture Inputs: Tri-state enable bit to output input, output clocks Outputs: input bit Internal FFs for input & output paths Fast/Slow outputs 5 ns vs. 30 ns rise Pull-up used with unused IOBs
Enable Output

Program Controlled Options OUT INV TS INV OUTPUT SOURCE SLEW RATE PASSIVE PULLUP Vcc

MUX Out D Q Output Buffer

PAD

Direct In Q Registered In

D TTL or CMOS Input Buffer R

Clocks

Global Reset

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture Configurable Logic Block: CLB

2 FFs Any function of 5 Variables Global Reset Clock, Clock Enb

Reset DIN Mux D RD Q CE

Q1 A B C D E

Mux

Combinational Function Generator Q2 G Mux D RD Q CE Mux Y

Clock

Mux

Independent DIN

Clock Enable

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture CLB Function Generator

Q1 A B Mux Mux Mux Q2 Q1 A B C D E Mux Mux Mux

Function of 4 Variables Function of 4 Variables

Q1 A B Mux
Function of 5 Variables

C Mux D E Q2

C D E

Any function of 5 variables

Q2 Two Independent Functions of 4 variables each

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture CLB Function Generator

Q1 A B C D
Certain Limited Functions of 6 Variables

Mux Mux
Function of 4 Variables

E F Mux G

Q2 Q1 A B C D Q2 Mux Mux
Function of 4 Variables

Implementation Strategies Designing with More Sophisticated PLDs Xilinx Application Examples 5-Input Parity Generator Implemented with 1 CLB: F = A xor B xor C xor D xor E

2-bit Comparator: A B = C D or A B > C D Implemented with 1 CLB: (GT) F = A C + A B D + B C D

(EQ) G = A B C D + A B C D + A B C D + A B C D

Implementation Strategies Designing with More Sophisticated PLDs Xilinx Application Examples n-Input Majority Circuit Assert 1 whenever n/2 or greater inputs are 1
5-input Majority Circuit 9 Input Parity Logic CLB CLB

7-input Majority Circuit CLB CLB CLB CLB

n-input Parity Functions 5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs!

Implementation Strategies Designing with More Sophisticated PLDs Xilinx Application Examples 4-bit Binary Adder
A3 B3 A2 B2 A1 B1 A0 B0 Cin

CLB

CLB

CLB

CLB

Full Adder, 4 CLB delays to final carry out

S0

Cout

S3

C2

S2

C1

S1

C0

A3 B3 A2 B2

A1 B1 A0 B0 Cin

CLB S3 Cout

S2

CLB S1 C2

2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

S0

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture Interconnect Direct Connections Global Long Line Horizontal/Vertical Long Lines Switching Matrix Connections
Horizontal Long Line DI CE A B X C CLB2 K Y E D R DI CE A B X C CLB3 K Y E D R Horizontal Long Line Switching Matrix Direct Connections DI CE A B X C CLB0 K Y E D R DI CE A B X C CLB1 K Y E D R

Vertical Long Lines

Global Long Line

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture Implementing the BCD to Excess 3 FSM Q2+ = Q2 Q0 + Q2 Q0 Q1+ = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0

Q0+ = Q0
Z = Z Q1 + X Q1

No function more complex than 4 variables 4 FFs implies 2 CLBs

Synchronous Mealy Machine Global Reset to be used Place Q2+, Q0+ in once CLB Q1, Z in second CLB maximize use of direct & general purpose interconnections

Implementation Strategies Design with More Sophisticated PLDs Xilinx LCA Architecture Implementing the BCD to Excess 3 FSM
Clk Clk

CE CE DI B C Y K E D RES Q0 FG Q0 Q2 Q0 FG A X DI Q2 B C K E D RES CE X Q2 Q1 Q0 X Q1 A X FG Q1

Y FG

CLB1

CLB2

Design Case Study Traffic Light Controller Decomposition into primitive subsystems Controller FSM next state/output functions state register

Short time/long time interval counter

Car Sensor

Output Decoders and Traffic Lights

Design Case Study Traffic Light Controller Block Diagram

Reset Clk

short time/ long time counter TL controller fsm Next State Output Logic 2 2 State Register ST F Encoded Light Light Decoders Signals 3 3 H 2 2

TS Reset C (async) Clk Car Sensor C (sync)

Design Case Study Traffic Light Controller Subsystem Logic

+ Ci n Present D Q RQ \Prese nt +
H0 0 0 1 FG FY FR

Light Decoders
C

F0 F1 1

2 A 3 B G

Y0 Y1 Y2 Y3

4 5 6 7 1 0 0

139a

\Reset

HG HY HR

CL K

Car Detector
+

H1

1 A Y0 1 4 B Y1 3 Y2 1 G Y3 5 139b

1 1 2 1 9 0

Interval Timer

CLK

Reset ST

7 P 10 T 163 1 2 CLK RCO 5 6 D QD 11 5 C QC 12 4 B QB 13 3 A QA 14 9 LOAD CLR 1 CLR

TL

TS

Design Case Study Traffic Light Controller Next State Logic State Assignment: HG = 00, HY = 10, FG = 01, FY = 11 P1 = C TL Q1 + TS Q1 Q0 + C Q1 Q0 + TS Q1 Q0 P0 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0 ST = C TL Q1 + C Q1 Q0 + TS Q1 Q0 + TS Q1 Q0 HL[1] = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0 HL[0] = TS Q1 Q0 + TS Q1 Q0 FL[1] = Q0 FL[0] = TS Q1 Q0 + TS Q1 Q0 PAL/PLA Implementation: 5 inputs, 7 outputs, 8 product terms PAL 22V10 -- 11 inputs, 10 prog. IOs, 8 to 14 prod terms per OR ROM Implementation: 32 word by 8-bit ROM (256 bits) Reset may double ROM size

Design Case Study Traffic Light Controller Next State Logic Counter-based Implementation
1 GA 3 A3 4 A2 5 A1 6 A0 13 12 11 10 B3 B2 B1 B0

2 x 4:1 MUX

HG TLC / ST HY TS / ST

153
YA 7 ST 7 10 P 163 T 15 2 CLK RCO 6 5 4 3 D C B A QD QC QB QA 11 12 13 14

TS TL \C TL C

YB 9

Q1 Q0

FG
TL+C / ST FY TS / ST

15 GB

S1 SO 2 14

9 LOAD \Reset 1 CLR

TTL Implementation with MUX and Counter

Can we reduce package count by using an 8:1 MUX?

ST = Count

Design Case Study Traffic Light Controller Next State Logic Counter-based Implementation

Dispense with direct output functions for the traffic lights

Why not simply decode from the current state?
HG HY HR 1 1 G Q1 Q0 3B 2A Y3 Y2 Y1 Y0 7 6 5 4 0 0 FG FY FR 0 0 1

139a

ST is a Synchronous Mealy Output Light Controllers are Moore Outputs

Design Case Study Traffic Light Controller LCA-Based Implementation Discrete Gate Method: None of the functions exceed 5 variables P1, ST are 5 variable (1 CLB each) P0, HL1, HL0, FL0 are 3 variable (1/2 CLB each) FL1 is 1 variable (1/2 CLB) 4 1/2 CLBs total!

Design Case Study Traffic Light Controller LCA-Based Implementation

TL C TS TS

TS Q0

DI CE A B X C F0 K Y E D R

Q1

DI CE A B X C K Y E D R

F1 Q0

Q1

Placement of functions selected to maximize the use of direct connections

Q0 TS TL
DI CE A B X C Q1 K Y E D R

Q1 TS
DI CE A B X C K Y E D R

Q0 H1 H0

Q1 TL TS C Q0
DI CE A B X C ST K Y E D R DI CE A B X C K Y E D R

Design Case Study Traffic Light Controller

LCA-Based Implementation
Counter/Multiplexer Method: 4:1 MUX, 2 Bit Upcounter MUX: six variables (4 data, 2 control) but this is the kind of 6 variable function that can be implemented in 1 CLB! 2nd CLB to implement TLC and TL + C' But note that ST/Cnt is really a function of TL, C, TS, Q1, Q0 1 CLB to implement this function of 5 variables! 2 Bit Counter: 2 functions of 3 variables (2 bit state + count) Also implemented in one CLB Traffic light decoders: functions of 2 variables (Q1, Q0) 2 per CLB = 3 CLB for the six lights Total count = 5 CLBs

Summary Optimization and Implementation of FSM

State Reduction Methods: Row Matching, Implication Chart

State Assignment Methods: Heuristics and Computer Tools Implementation Issues Choice of Flipflops Structured Logic Methods ROM based PLA/PAL based Jump Counter Methods Sophisticated PLDs: Altera, Actel, Xilinx