Professional Documents
Culture Documents
CHANDIGARH
Hardware +Software In Embedded system only one specific application software is loaded into ROM that controls the whole hardware system. e.g.- Mouse,Telephone,TV,VCR,Toys,FAX,Copier, Mobile etc.
The Atmel AVR is a family of RISC micro controllers from ATMEL. The AVR architecture was conceived by two students at the Norwegian Institute of Technology and further refined and developed at Atmel Norway. The AVR is a Harvard Architecture CPU.
The acronym AVR has been reported to stand for: Advanced Virtual RISC and also for the chip's designers: Alf-Egil Bogen and Vegard Wollan who designed the basic architecture at the Norwegian Institute of Technology.
RISC stands for reduced instruction set computer. CPU design with a reduced instruction set as well as a simpler set of instructions.
Harvard Architecture
Low Power RISC Architecture 32x8 General Purpose Working Registers 118 Instructions Most Single Cycle Flash Program Memory 2K 128K Internal SRAM In-system programmable EEPROM Internal calibrated RC Oscillator Power on Reset, Watch Dog Timer Supports many power saving modes Operating Voltage 2.7 5.5 V Speed Grade --- 0 16 MHz Bit Addressable I/O ports.
Instruction Pipelining Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle.
The five different addressing modes for the data memory cover:1. Direct 2 . Indirect with Displacement 3 . Indirect 4 . Indirect with Pre-decrement
AVR Registers
The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches to Y- or Z-register. When using register indirect addressing modes with pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
AVR Interrupts
The AVR provides several different interrupt sources. Each interrupt have a separate program vector in the program memory space. All interrupts are assigned individual enable bits. Enable bit is stored in the Status Register in order to enable the interrupt.
I/O ports
Three I/O memory address locations are allocated for each port: Data Register PORT x, Data Direction Register DDR x, and the Port Input Pins PIN x. (x=port name) The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write.
3. Power-down,
4. Power-save, 5. Standby,
6. Extended Standby.
Speed is Up to 16 MIPS EEPROM Memory ISP: In System Programming Very Powerful(high sampling rate) Internal RC oscillator
8051 microcontroller
AVR microcontroller