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Data 100ppm
Ethernet PHY
Ethernet PHY
100ppm
~
2
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Synchronous Ethernet
As services over Ethernet changed to constant bit rates and real-time, synchronization became required
Eg. Live Video, Audio services Eg. Support for Mobile Back haul
PLL
PLL
SyncE TCXO
System Clock
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Relevant Standards
G.8010 defines functional architecture of Ethernet networks G.803 describes architecture of transport networks based on SDH
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Implementations
PLL implementations are almost always digital
Low loop bandwidths in the analogue domain are difficult Digital offers additional features
Input Clock monitoring Reference Switching
Recovered Clocks
Loop Filter
DCO
Oscillator
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Freerun Accuracy
When the system operates by itself, what is output frequency accuracy?
The DCO (Digitally Controlled Oscillator) freerun output will be output accuracy Since DCO is driven by Oscillator and therefore its accuracy will be the oscillators This is different from Holdover, as Holdover is after disciplining the DCO to a value
Loop Filter
DCO
Oscillator
EEC oscillators to be at 4.6ppm, accuracy including all deviations Stratum 3 and Stratum 3E accuracies are at 4.6ppm Pluto/+ and RTX family of TCXOs and Mercury OCXOs 90% applications only need TCXOs
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Wander Generation
Ideal input is applied at the input and output variation is measured
Under a constant temperature and a temperature ramp
Loop Filter
DCO
Oscillator
For Output stability (MTIE & TDEV) to be below mask, Oscillator temperature performance to be tested
Option 2 loop bandwidth is 0.1Hz, time constant of 1.6s, TCXO may be challenged for temperature stability
Slope performance (ppb/C) is important
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Some applications with extreme temperature variation conditions may call for an OCXO
This depends on the customer application requirement The Mercury and/or an oscillator from the traditional OCXO family (i.e. ROX5022) should be used
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Jitter Performance
The PLL could be directly driving the PHY reference clock
Oscillator to PLL output multiplication, Clock multiplication inside the PHY, Electrical to Optical conversion, power supply variations and layout design - all adds to additional jitter and these effects need to be considered Eg. 10G PHY needs <1ps, Oscillator needs to be ~500fs
Ethernet PHY
The requirement for jitter is on the line output which depends on the PHY reference clock jitter from the PLL, which in turn depends on the Oscillator jitter to the PLL
PLL
SyncE TCXO
System Clock
The RPT7050/5032x family can support 10H PHY designs with many of the Timing Silicon Chipsets
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Holdover Requirements
Holdover System output is held constant when input is lost. Defined by: Initial holdover accuracy Oscillator temperature stability +/- 50 PPB +/- 2 PPM Best case system accuracy Usualy -40 to +85 deg C Only for option 2 Occurs because of entry to holdover
Oscillator Aging
Other effects (Vss, load, etc.) Initial phase jump
Loop Filter
DCO
Output Synthesi zers Output TIE is to be limited by Oscillator temperature behaviour, aging and drift
Oscillator
Wander Generation
F v T performance and aging need to be excellent Most variations will be filtered by PLL, but quick variations will pass through
Jitter generation
Lower the jitter, the better
Holdover
F v T performance, aging and drift parameters are critical
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IDT
8vxxxx family of devices
Microsemi Corporation
ZL3014x family, ZL3016x family devices
Semtech
ACS95xx family of devices
Silicon Labs
Si9528 family of devices
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Summary
Rakon Pluto/+ and RTX family TCXOs and Mercury family OCXOs are well qualified for Synchronous Ethernet applications supporting ITU-T G.8262 standards Rakon has worked with all Timing Silicon vendors to qualify oscillator solution for Synchronous Ethernet Rakon has wide range of oscillators to support customers based on specific requirements
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The End
Thank you
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