Manufacturing Process

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al. and presentation by J.Christiansen/CERN]
EE415 VLSI Design

Fabrication
Masks

Chips Processing Processed Wafer

Wafers

EE415 VLSI Design

Traditional CMOS Process

EE415 VLSI Design

A Modern CMOS Process

Dual-Well Trench-Isolated CMOS
gate oxide field oxide Al (Cu) SiO2 tungsten

TiSi2

p well p-epi n+ p-

n well p+

SiO2

Epi-layer is a high quality crystal grown on the polished surface of pre-doped silicon wafers for EE415 VLSI Design making CMOS nano devices.

Photo-Lithographic Process
oxidation optical mask

photoresist removal (ashing)

photoresist coating
stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]).

acid etch process step spin, rinse, dry

photoresist development

EE415 VLSI Design

Growing the Silicon Ingot

From Smithsonian, 2000

EE415 VLSI Design

E-Beam Lithography

As the miniaturization of IC devices continues, electron beam exposure technology is gaining prominence as a technology for nextgeneration design rules

From: ADVANTEST CORPORATION

EE415 VLSI Design

Silicon Oxidation

The oxide is grown by exposing the silicon surface to high temperature steam. As the oxide grows, the silicon is consumed. The arrows represent the direction of motion of each surface of the oxide. Underneath the nitride mask, the growth is suppressed, and these areas will become the active transistor area.
EE415 VLSI Design

Source: Bell Laboratories

Patterning - Photolithography
UV light

1. 2. 3. 4.

Oxidation Photoresist (PR) coating Stepper exposure SiO2 Photoresist development and bake 5. Acid etching
Unexposed (negative PR) Exposed (positive PR)

mask

PR

6. Spin, rinse, and dry 7. Processing step

Ion implantation Plasma etching Metal deposition

8. Photoresist removal (ashing)

EE415 VLSI Design

CMOS Process at a Glance

Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon exception! 3 source and drain diffusions

Create contact and via windows Deposit and pattern metal layers
EE415 VLSI Design

1 tubs (aka wells, active areas)

Example of Patterning of SiO2

Chemical or plasma etch
Si-substrate Si-substrate Hardened resist SiO 2

Silicon base material

Photoresist SiO2
Si-substrate

4. After development and etching of resist, chemical or plasma etch of SiO2

Hardened resist SiO2 Si-substrate

1&2. After oxidation and deposition of negative photoresist

UV-light Patterned optical mask Exposed resist Si-substrate

5. After etching
SiO2 Si-substrate

EE415 VLSI Design

3. Stepper exposure

8. Final result after removal of resist

Diffusion and Ion Implantation

1. Area to be doped is exposed (photolithography) 2. Diffusion or Ion implantation

EE415 VLSI Design

Ion Implantation
1. Dopant atoms are ionized and then accelerated by an electric field until they impinge on the silicon surface, where they embed themselves. A polysilicon line crosses the active area in the upper left and forms the gate of a transistor. Source: Bell Laboratories
EE415 VLSI Design

2.

Deposition and Etching

1. Pattern masking (photolithography) 2. Deposit material over entire wafer
CVD (Si3N4) chemical deposition (polysilicon) sputtering (Al)

3. Etch away unwanted material

wet etching dry (plasma) etching
EE415 VLSI Design

Metallization
1. First an insulating glass layer is deposited to cover the silicon, then contact holes are cut into the glass layer down to the silicon. Metal is deposited on top of the glass, connecting to the devices through the contact holes. The graphic shows a snapshot during the filling of a contact hole with aluminum. Source: Bell Laboratories
EE415 VLSI Design

2.

3.

F5112 E-Beam Lithography

Single-Column System Minimum Feature Size: 100nm

Overlay Accuracy: |mean|+3 sigma<=40nm 3 sigma<=15nm

Block Exposure Method: Max. No. of Block Patterns: 70

EE415 VLSI Design

Planarization: Polishing the Wafers

From Smithsonian, 2000

EE415 VLSI Design

Self-Aligned Gates
1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant
EE415 VLSI Design

Simplified CMOS Inverter P-well Process

cut line

p well
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P-Well Mask

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Active Mask

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Poly Mask

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P+ Select Mask

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N+ Select Mask

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Contact Mask

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Metal Mask

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VLSI Fabrication: The Cycle

EE415 VLSI Design

CMOS N-well Process (contd)

The n-well CMOS process starts with a moderately doped (impurity concentration less than 1015 cm-3) p-type silicon substrate. Then, an oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. This defines, the active areas of the nMOS and pMOS transistors. Thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are critical fabrication parameters, since they affect the characteristics of the MOS transistor, and its reliability.

EE415 VLSI Design

CMOS N-well Process (contd)

The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step.

EE415 VLSI Design

CMOS N-well Process (contd)

Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. The ohmic contacts to the substrate and to the n-well are implanted in this process step.

EE415 VLSI Design

CMOS N-well Process (contd)

An insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows.

EE415 VLSI Design

CMOS N-well Process (contd)

Metal is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is nonplanar, the quality and the integrity of the metal lines created in this step are very critical and are essential for circuit reliability.

EE415 VLSI Design

CMOS N-well Process (contd)

The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (builtin n-well), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (overglass for protection) over the chip, except for wire-bonding pad areas.

EE415 VLSI Design

Advanced Metallization

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From Design to Reality

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Design Rules

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CMOS Process Layers

Layer
Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via

Color
Yellow Green Green Red Blue Magenta

Representation

Black
Black Black

EE415 VLSI Design

Layers in 0.25 mm CMOS process

EE415 VLSI Design

Design Rules

Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width
scalable design rules: lambda parameter absolute dimensions: micron rules

Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes
set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers
EE415 VLSI Design

3D Perspective
Polysilicon Aluminum

EE415 VLSI Design

Why Have Design Rules?

To be able to tolerate some level of fabrication errors such as 1. Mask misalignment

2. Dust 3. Process parameters (e.g., lateral diffusion) 4. Rough surfaces

EE415 VLSI Design

Intra-Layer Design Rule Origins

Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab
0.3 micron
0.15 0.15 0.3 micron

EE415 VLSI Design

Inter-Layer Design Rule Origins

1.

Transistor rules transistor formed by overlap of active and poly layers

Transistors
Catastrophic error

Unrelated Poly & Diffusion

Thinner diffusion, but still working

EE415 VLSI Design

Inter-Layer Design Rule Origins, Cont

2.

Contact and via rules

M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My

Contact Mask Via Masks mask misaligned

both materials

0.3

Contact: 0.44 x 0.44

0.14

EE415 VLSI Design

Intra-Layer Design Rules

Same Potential Well 10 Active 3 2 Select 3 Contact or Via Hole 2 2 Metal1 3 0 or 6 Different Potential 9 Polysilicon 2 3 2

Metal2

3
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Transistor Layout

Transistor

EE415 VLSI Design

Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

EE415 VLSI Design

Select Layer
2 3 1 3 3 2 Select

Substrate
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Well

IC Layout

EE415 VLSI Design

CMOS Inverter Sticks Diagram

V DD In
3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program

1
GND
Stick diagram of inverter
EE415 VLSI Design

CMOS Inverter max Layout

Out metal1 metal2 In metal1-poly via

polysilicon
VDD

pfet
pdif metal1-diff via PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) ndif nfet GND
EE415 VLSI Design

metal2-metal1 via

Layout Editor

EE415 VLSI Design

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

EE415 VLSI Design

CMOS Inverters
VDD PMOS

1.2mm =2l In Out Metal1 Polysilicon

NMOS GND
EE415 VLSI Design

Layout Design Rule Violation

Well-well spacing = 9 M1width = 4 M1- M1 spacing = 3 Active to well edge = 5 Min active width = 3 Poly overlap of active = 2 M2 - M2 spacing = 4 All distances in l

EE415 VLSI Design

Building an Inverter
Step 1 Step 2 Step 3 Step 4

VCC P VCC Output

P diffusion Output N diffusion

VSS

Output

VSS

EE415 VLSI Design

With permission of William Bradbury

Building a 2 Input NOR Gate

A Out B Step 1 Step 2 Step 3 Step 4

P V C C

S h a r e d n o d e

O u t p u t

V C C

O u t p u t

A B

P Shared node P Output

V S S N A B A B A

O u t p u t B

V S S

V S S

EE415 VLSI Design

With permission of William Bradbury

Building a 2 Input NAND Gate

A Step 1 Step 2 Step 3 Step 4

Out
B P V C C S h a r e d n o d e V S S N A B A B A O u t p u t B V S S O u t p u t

V C C

A A B

B Output

N Shared node N

O u t p u t

V S S

EE415 VLSI Design

With permission of William Bradbury

Combining Logic Functions

A
Out B B VCC VCC VCC

B P B B A B N N P Out

B VSS

Out

Out

VSS

VSS

EE415 VLSI Design

With permission of William Bradbury

Cell Symbol to Logic to Transistor Schematic to Layout

LD LD SRAM BIT TRANSISTOR SCHEMATIC OUTPUT

OUTPUT
LD
P2, 1.8 P4, 2.0 B N4, 2.0

INPUT

SRAM

INPUT
P1, 1.4 N1, 1.4 LD A

N2, 2.0

SRAM BIT LOGIC LD INPUT P 1.4 N 1.4 P 1.8 N 2.0 A

P3, .5/1.0

B P 2.0 N 2.0

OUTPUT

N3 , .6/1.0

LD

P .5/1.0 N .6/1.0

Minimum poly width L = 0.20

Note the listing of the L dimension which is not the minimum defined by the process

EE415 VLSI Design

With permission of William Bradbury

Schematic to Transistor
A LD OUTPUT B

P1
INPUT A

P2
VCC

P4

VCC

B OUTPUT

N1
INPUT A B

N2
VSS

N4

VSS

LD

N3
B

VSS

VCC A B

P3

EE415 VLSI Design

With permission of William Bradbury

Assembling the Transistors by Type and Node Name

A B B VCC LD INPUT A VC C OUTPUT

A B

VCC

INPUT B

VSS

B OUTPUT

A VSS LD B VSS

EE415 VLSI Design

With permission of William Bradbury

Connecting the Nodes

A B B VCC LD INPUT A VC C OUTPUT

A B

VCC

INPUT B

VSS

B OUTPUT

A VSS LD B VSS

EE415 VLSI Design

With permission of William Bradbury

Connecting the Dotes

A B LD I N P U T V C C VC C B O U T P U T

V C C

UNMERGED DATA: INPUT I N P A U T LD A

V S S A
B VSS

Notice the addition of contacts where necessary and also the use of redundant contacts to improve reliability
EE415 VLSI Design

O V U SS T P U T B

With permission of William Bradbury

Cleaning Connections and Completing the layout

.

N-WELL

Added: 1.Taps 2.Implants 3.Cell boundry

A P-IMPLANT B

N-TAP

P2
LD
DD IN P A U T

P1

V C C A

P C 3 B B C
B

O VC U C T P U BT

P4

INPUT
IN PU A T

N1

N3
B

VS S

B B

OUTPUT

N4
OU TP VS UT S

LD
N-IMPLANT

N2
VS S

EE415 VLSI Design

P-TAP With permission of William Bradbury

Using sticks
VCC

Metal1 P diffusion Output N diffusion

Poly
Contact

VSS B
EE415 VLSI Design

A
With permission of William Bradbury

Same cell, different shape

.

VCC
VCC

Output

VCC

VCC

Out

VSS B B A
VSS

Out

B VSS

EE415 VLSI Design

With permission of William Bradbury

Cells Designed for Sharing

. Sense Ckt. for One Row Memory Row 1 Reference Voltage Compare Row 1 Height of 1 Memory Bit 1 Bit 1 Bit

Dual Sense Amp Cell Height

Memory Row 1 Reference Voltage Compare Row 1

Compare Row 2 Reference Voltage Memory Row 2

1 Bit 1 Bit

Dual Sense Amps

Dual Write Line Ckts

Courtesy Mentor Graphics Corp. Layout created using IC-Station.

EE415 VLSI Design

With permission of William Bradbury

Cells Designed for Sharing

.

EE415 VLSI Design

With permission of William Bradbury

Packaging

EE415 VLSI Design

Packaging Requirements
Desired package properties

Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap
Only periphery of chip available for IO connections

Wire bonding

Mechanical bonding of one pin at a time (sequential)

Cooling from back of chip High inductance (~1nH)
EE415 VLSI Design

More about packaging:

http://www.embeddedlinks.com/chipdir/package.htm

Chip to package connection

Flip-chip
Whole chip area available for IO connections Automatic alignment One step process (parallel) Cooling via balls (front) and back if required Thermal matching between chip and substrate required Low inductance (~0.1nH)

EE415 VLSI Design

Bonding Techniques
Wire Bonding

Substrate Die Pad

Lead Frame

EE415 VLSI Design

Tape-Automated Bonding (TAB)

Sprocket hole Film + Pattern Test pads Lead frame Die Solder Bump

Substrate (b) Die attachment using solder bumps.

Polymer film (a) Polymer Tape with imprinted wiring pattern.

EE415 VLSI Design

New package types

BGA (Ball Grid Array)

Small solder balls to connect to board small High pin count Cheap Low inductance

Package inductance: 1 - 5 nH

CSP (Chip scale Packaging)

Similar to BGA Very small packages

EE415 VLSI Design

Flip-Chip Bonding
Die Solder bumps Interconnect layers

Substrate

EE415 VLSI Design

Package-to-Board Interconnect

(a) Through-Hole Mounting

(b) Surface Mount

EE415 VLSI Design

Package Types

Through-hole vs. surface mount

EE415 VLSI Design

From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Chip-to-Package Bonding

Traditionally, chip is surrounded by pad frame

Metal pads on 100 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling

EE415 VLSI Design

From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Advanced Packages

Bond wires contribute parasitic inductance Fancy packages have many signal, power layers
Like tiny printed circuit boards

Flip-chip places connections across surface of die rather than around periphery
Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!) Heated to melt balls Also called C4 (Controlled Collapse Chip Connection)
From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

EE415 VLSI Design

Package Parasitics

Use many VDD, GND in parallel

Inductance, IDD
Package

Chip VDD Chip Chip GND

Bond Wire

Lead Frame

Board VDD

EE415 VLSI Design

Signal Pins

Signal Pads

Package Capacitor Board GND

From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Signal Interface

Transfer of IC signals to PCB

Package inductance. PCB wire capacitance. L - C resonator circuit generating oscillations. Transmission line effects may generate reflections Cross-talk via mutual inductance
L-C Oscillation
f =1/(2p(LC)1/2) L = 10 nH C = 10 pF f = ~500MHz R Transmission line reflections

Chip

PCB trace L Z

Package

EE415 VLSI Design

Package Parameters

EE415 VLSI Design

Package Parameters

EE415 VLSI Design

Package Parameters
2000 Summary of Intels Package I/O Lead Electrical Parasitics for Multilayer Packages

EE415 VLSI Design

Packaging Faults

EE415 VLSI Design

Small Ball Chip Scale Packages (CSP) Open

Packaging Faults

EE415 VLSI Design

CSP Assembly on 6 mil Via in 12 mil pad Void over via structure

Miniaturisation of Electronic Systems

Enabling

Technologies :

SOC High Density Interconnection technologies

SIP System-in-a-package

EE415 VLSI Design

From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

The Interconnection gap

Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends

PCB scaling Advanced PCB

Laser via

IC scaling

Interconnect Gap

EE415 VLSI Design

Time

From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

The Interconnection gap

Requires new high density Interconnect technologies

PCB scaling Advanced PCB

IC scaling

Thin film lithography based Interconnect technology Reduced Gap

EE415 VLSI Design

Time

From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

SoC has to overcome

Technical Challenges:

Increased System Complexity. Integration of heterogeneous IC technologies. Lack of design and test methodologies.
Long Design and test cycles High risk investment Hence time to market. System-in-a-Package
From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

Business Challenges:

Solution

EE415 VLSI Design

Multi-Chip Modules

EE415 VLSI Design

Multiple Chip Module (MCM)

Increase integration level of system (smaller size) Decrease loading of external signals > higher performance No packaging of individual chips Problems with known good die: Single chip fault coverage: 95% MCM yield with 10 chips: (0.95)10 = 60% Problems with cooling Still expensive

EE415 VLSI Design

Complete PC in MCM

EE415 VLSI Design