CMOS Sequential Circuit Design

Sequential circuits : the output depends on previous as well as current inputs; said to have state. Examples: FSM, Pipelines. Usually designed with flip-flops or latches (memory elements), that hold data called tokens. Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens. Makes circuit slower than just the logic delay called sequencing overhead, also called as clocking overhead.

Sequencing the static and dynamic circuits. Static circuits : gates that have no clock input, examples: complementary CMOS, pseudo-nMOS, pass transistor logic. Dynamic circuits :gates that have a clock input, e.g. domino logic. Sequencing elements : static or dynamic. Static storage : Feedback to retain its output value indefinitely. Dynamic storage: Maintains its value as charge on a capacitor that will leak away if not refreshed for a long period of time.

Sequencing Static Circuits

Sequential elements: flip-flops and latches. 3 terminals incorporated by both: data input (D), clock (elk), and data output (Q). The latch is transparent when the clock is high and opaque when the clock is low level sensitive. The flip-flop: an edge-triggered device that copies D to Q on the rising edge of the clock and ignores D at all other times.

Sequencing Methods
Flip-flops
Tc

Flop

Combinational Logic

2-Phase Latches

1 tnonoverlap 2 1 Tc/2 2 1 Combinational Logic Half-Cycle 1 tnonoverlap

Latch

Latch

Combinational Logic Half-Cycle 1

Pulsed Latches

tpw p p Combinational Logic

Latch

Latch

Latch

Flop

Flip-Flops 2-Phase Transparent Latches Pulsed Latches

clk clk clk

Flip Flop viewed as back to back latch pair

Timing Diagrams
Contamination and Propagation Delays
tpd tcd tpcq tccq tpdq tpcq tsetup thold Logic Prop. Delay Logic Cont. Delay Latch/Flop Clk-Q Prop Delay Latch/Flop Clk-Q Cont. Delay Latch D-Q Prop Delay Latch D-Q Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time
D clk
Latch

A A Combinational Logic Y Y tcd

tpd

clk D
Flop

clk Q D

tsetup

thold

tpcq Q tccq

clk D

tccq tpcq Q

tsetup tpdq

thold

tcdq Q

Max-Delay Constraints
Ideally, the entire clock cycle would be available for computations in the combinational logic. The sequencing overhead of the latches or flip-flops cuts into this time. If the combinational logic delay is too great, the receiving element will miss its setup time and sample the wrong value. This is called a setup time failure or max-delay failure. It can be solved by : redesigning the logic to be faster or by increasing the clock period. The computation of the actual time available for logic and the sequencing overhead of each of sequencing elements is done in next slides: flip-flops, two-phase latches, and pulsed latches.

Max-Delay: Flip-Flops
t pd Tc

clk
F1

clk Combinational Logic Tc

F2

sequencing overhead

Q1

D2

clk Q1 D2

tpcq tpd

tsetup

Max-Delay: Flip-Flops
t pd Tc tsetup t pcq
sequencing overhead

clk
F1

clk Combinational Logic Tc

F2

Q1

D2

clk Q1 D2

tpcq tpd

tsetup

Max Delay: 2-Phase Latches

1
L1

2 Q1 Combinational Logic 1
L2

1 Q2 Combinational Logic 2
L3

D1

D2

D3

Q3

t pd t pd 1 t pd 2 Tc

sequencing overhead 1

Tc D1 Q1 D2 Q2 D3 tpdq1 tpd1 tpdq2 tpd2

Max Delay: 2-Phase Latches

Solving for the maximum logic delay, which is the sum of the logic delays through each of the two phases. The sequencing overhead is the two latch propagation delays. The nonoverlap between clocks does not degrade performance in the latch-based system because data continues to propagate through the combinational logic between latches even while both clocks are low. A flip-flop can be made from two latches whose delays determine the flop propagation delay and setup time.

Max Delay: 2-Phase Latches

1
L1

2 Q1 Combinational Logic 1
L2

1 Q2 Combinational Logic 2
L3

D1

D2

D3

Q3

t pd t pd1 t pd 2 Tc

2t
pdq sequencing overhead

1 2 Tc D1 Q1 D2 Q2 D3 tpdq1 tpd1 tpdq2 tpd2

Max Delay: Pulsed Latches

t pd Tc max
sequencing overhead

p
L1

p Combinational Logic Tc
L2

D1

Q1

D2

Q2

D1 (a) tpw > tsetup Q1 D2 p

tpdq tpd

tpcq Q1 (b) tpw < tsetup D2 tpd

Tc

tpw tsetup

Max Delay: Pulsed Latches

p p Combinational Logic Tc D1 (a) tpw > tsetup Q1 D2 p tpcq Q1 (b) tpw < tsetup D2 tpd Tc tpw tsetup tpdq tpd
L2

t pd Tc max t pdq , t pcq tsetup t pw

sequencing overhead

L1

D1

Q1

D2

Q2

Min-delay Constraints
Ideally, sequencing elements can be placed back to back without intervening combinational logic and still function correctly. e.g. , a pipeline can use back-to-back registers to sequence along an instruction opcode without modifying it. However, if the hold time is large and the contamination delay is small, data can incorrectly propagate through two successive elements on one clock edge, corrupting the state of the system. This is called a race condition, hold time failure, or min-delay failure. It can only be fixed by : redesigning the logic, not by slowing the clock. Therefore, designers should be very conservative in avoiding such failures because modifying and refabricating a chip is very expensive and time-consuming.

Min-Delay: Flip-Flops
clk
F1

tcd

Q1

CL

clk
F2

D2

clk Q1 tccq D2 tcd thold

Min-Delay: Flip-Flops

F1

tcd thold tccq

D2

clk Q1 CL

clk
F2

clk Q1 tccq D2 tcd thold

Min-Delay: Flip-Flops
If the contamination delay through the flip-flop exceeds the hold time, back-to-back flip-flops can be safely used. If not, explicitly delay must be added between the flip flops (e.g., with a buffer) or use special slow flip-flops with greater than normal contamination delay on paths that require backto-back flops. Scan chains are a common example of paths with back-to-back flops.

Min-Delay: 2-Phase Latches

tcd 1,tcd 2
1
L1

Q1

CL

Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches!

2
L2

D2

1 2

tnonoverlap

tccq

Q1 D2 thold

tcd

Min-Delay: 2-Phase Latches

tcd 1,tcd 2 thold tccq tnonoverlap
Hold time reduced by nonoverlap
2
L2

1
L1

Q1

CL

D2

Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!

1 2

tnonoverlap

tccq

Q1 D2 thold

tcd

Min-Delay: Pulsed Latches

tcd
Hold time increased by pulse width
p
L1

Q1

CL

p
L2

D2

tpw thold

Q1 tccq D2

tcd

Min-Delay: Pulsed Latches

tcd thold tccq t pw
p
L1

Q1

CL

Hold time increased by pulse width

p
L2

D2

tpw thold

Q1 tccq D2

tcd