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ARM

Advanced RISC Machine


Sivraj P. Asst. Professor Dept of EEE, ASE, Coimbatore

ARM Architecture

Brief History of ARM


Acorn - a Computer Manufacturer 1983: Acorn Limited: Dominant position in UK personal computer market with Rockwell 6502 (8- Bit) CPU. 1983: 16- Bit CISC CPUs slower than standard memory ports with long interrupt latencies 1983- 85: Acorn designed the first commercial RISC CPU: Acorn RISC Machine (ARM) 1990: Advanced RISC Machine was formed to broaden the market beyond Acorns product range
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Brief History of ARM


1990: Startup with 12 engineers and 1 CEO No patents, no customers, very little money Mid- 1990s: TI licensed ARM7 Incorporated into a chip for mobile phones RISC concept introduced in 1980 at Stanford & Berkley ARM Cores Licensed to partners to develop & fabricate new microcontrollers Soft-core

ARM Architecture

Licensees
Intel Corporation Texas Instruments Analog Devices Inc. Atmel Corporation STMicroelectronics Cirrus Logic Altera Freescale Semiconductor Toshiba Samsung Electronics NXP Zilog Qualcomm Renesas Fujitsu Infineon Technologies, Sony Atheros Communications

ARM Architecture

Architectural Inheritance from Berkeley RISC I


Used: Load- store architecture Fixed- length 32- bit instructions 3 address format Rejected: Register windows=> Costly Use Shadow Registers in ARM Delayed branches Single cycle execution of all instructions Memory Access Multiple Cycles when no separate data and instruction memory support Result: RISC with a few CISC features

ARM Architecture

ARM Architecture
Based on RISC Architecture with enhancements to meet requirements of Embedded applications
A Large Uniform Register File Load-Store Architecture, where data processing operates on register content only Uniform & fixed length Instructions 32-bit processor Instructions are 32-bit long Good Speed/Power Consumption Ratio High Code Density
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Enhancements to Basic RISC


Control over ALU & Shifter for every data processing operations to maximize their usage
Auto-Increment & Auto-Decrement Addressing Modes to optimize program loops Load & Store Multiple Instructions to maximize data throughput Conditional Execution of Instructions to maximize Execution throughput

ARM Architecture

ARM Architecture Versions


Version 1 (1983-1985)
26 bit Addressing, no Multiply or Coprocessor

Version 2
Includes 32-bit result multiply coprocessor

Version 3
32-bit Addressing

Version 4
Add Signed , Unsigned Half-word & Signed Byte Load & Store Instructions

Version 4T
16-bit Thumb - compressed form of Instructions
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Architecture Versions
Version 5T
Superset of 4T adding new Instructions

Version 5TE
Add Signal Processing Extension

Examples: ARM 6 : v3 ARM7 : v3 ARM7TDMI : v4T StrongArm : v4 ARM 9E-S : v5TE

ARM Architecture

Development of the ARM Architecture


Improved ARM/Thumb Interworking CLZ SA-110 SA-1110 Saturated maths DSP multiplyaccumulate instructions ARM1020E

1 2 3
Early ARM architectures

Halfword and signed halfword / byte support

5TE

Jazelle Java bytecode execution ARM9EJ-S ARM7EJ-S

5TEJ

System mode

ARM926EJ-S ARM1026EJ-S

Thumb instruction set ARM7TDMI ARM720T

SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support

4T
ARM9TDMI ARM940T

XScale ARM9E-S ARM966E-S

ARM1136EJ-S

ARM7TDMI
It is widely used across a range of application, notably in digital mobile telephones.

The origin of the name ARM7TDMI:

The THUMB 16-bit compressed instruction set. On-chip Debug support, enabling the processor to halt in response to a debug request. An enhanced Multiplier, with higher performance than its predecessors and yielding a full 64-bit result. 4 extra instructions are provided which performs 32 * 32 -> 64 multiplications and 32 * 32 + 64 -> 64 multiply and accumulate Embedded ICE hardware to give on-chip breakpoint and watch point support.

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Data Sizes & Instruction Sets


The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Half-word means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARMs implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set

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Overview : Core Data Path


Data Items are placed in Register File No Data Processing Instructions directly manipulate Data in memory Instructions Typically use two Source Registers & single result or Destination Registers A Barrel Shifter on the date path can pre-process data before It enters into ALU

Increment/Decrement Logic can update the Register Content for Sequential access independent of ALU
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Basic ARM Organization

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Registers
General Purpose Registers hold either Data or Address All Registers are of 32-bits In User Mode 16 Data Registers and 2 Status Registers are Visible

Data Registers : r0 to r15


Three Registers r13,r14 & r15 perform special functions
R13 : Stack Pointer R14 : Link Register ( Where return address is put whenever a subroutine is called) R15 : Program Counter
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Registers (2)
Depending upon the context, registers r13 & r14 can also be used as GPRs Any Instruction which use r0 can as well be used with anyother GPR (r1-r13)

In addition there are two Status Reisters


CPSR : Current Program Status Register SPSR : Saved Program Status Register

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Register : r15
When the Processor is executing in ARM state

All instructions are 32-bit wide


All instructions are word aligned PC value is stored in bits [31:2]cwith bits [1:0] undefined

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Program Status Register


CPSR : Monitors & Control Internal Operations
31

28 27

24

23

16

15

N Z C V Q

I F T

mode

Condition Code Flags

N Z C V

Set to 1 when result is negative Set to 1 when result is zero Set to 1 on carry or borrow generation and on shift operations Set to 1 if signed overflow occurs

Set to 1 if Saturation occurs


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ARM Architecture

Program Status Register


31

28 27

24

23

16

15

N Z C V Q

I F T

mode

I F

Disables IRQ interrupts when set

Disables FIQ interrupts when set


T=0 indicates ARM execution T=1 indicates Thumb execution
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ARM Architecture

Program Status Register


31

28 27

24

23

16

15

N Z C V Q

I F T

mode

Q Indicates occurrence of overflow and/or saturation M[4:0] 0b10000 0b10001 0b10010 0b10011 0b10111 0b11011 0b11111
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Mode User FIQ IRQ Supervisor Abort Undefined System


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Processor Modes
Processor Modes determine Which registers are Active Access Rights to CPSR Register itself Each Processor Mode is either Privileged : Full Read-Write access to the CPSR Non-Privileged : Only Read access to the Control Field of CPSR but Read-Write access to the Condition Flags
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Processor Modes (2)


ARM has Seven Modes

Privileged : Abort, Fast Interrupt Request (FIQ), Interrupt Request (IRQ), Supervisor, System & Undefined
Non-Privileged : User User Mode is used for Programs and Applications

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Privileged Modes
Abort : When there is a failed attempt to access memory

Fast Interrupt Request (FIQ) & Interrupt Request : Correspond to Interrupt levels available on ARM Supervisor Mode : State after Reset and generally the mode in which OS kernel executes

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Privileged Modes (2)


System Mode : Special Version of User Mode that allows Full Read-Write access of CPSR Undefined : When the Processor encounters an Undefined Instruction

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Banked Registers
Register File contains in all 37 Registers
20 Registers are hidden from Program at different times These registers are called Banked Registers

Banked Registers are available only when the Processor is in a particular Mode
Processor Modes (other than System Mode) have a set of associated banked registers that are subset of 16 registers Maps one-to-one onto a User Mode register

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Register Banking

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SPSR
Each Privileged Mode (except System Mode) has Associated with it a Save Program Status Register, or SPSR This SPSR is used to save the state of CPSR when the Privileged Mode is entered in order that the user state can be fully restored when the user process is resumed

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Register Organization

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Mode Changing
Mode changes by writing directly to CPSR or by Hardware when the processor responds to Exception or Interrupt To return to User Mode a special return instruction is used that instructs the core to restore the original CPSR & Banked Registers

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ARM Memory Organization

bit 31

bit 0

bit 0

bit 31

byte 3 byte 2 byte 1 byte 0 little-endian


ARM Architecture

byte 0 byte 1 byte 2 byte 3 big-endian


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Instructions
Instructions Process Data held in Registers and Access Memory with Load & Store instructions
Classes of Instructions
Data Processing Branch Instructions Load-Store Instructions Software Interrupt Instruction Program Status Register Instructions

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Features of ARM Instr. Set


3-Address Data Processing Instructions Conditional Execution of every Instruction Load & Store Multiple Registers Shift, ALU operation in a Single Instruction Open Instruction Set Extension through the Coprocessor Instruction

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ARM Data Types


Word is 32 bits long
Word can be divided into four 8-bit bytes ARM addresses can be 32 bits long Address refers to byte
Address 4 starts at byte 4

Can be configured at Power-Up as either little or Big-Endian Mode

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Data Processing
Manipulate Data within Registers
MOVE Instructions Arithmetic Instructions Multiply Instructions Logical Instructions Comparison Instructions

Suffix S on Data Processing Instructions Updates flags in CPSR

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Data Processing Instructions


Operands are 32-bit wide; come from registers or specified as literal in the instruction itself Second operand sent to ALU via Barrel Shifter 32-bit result placed in register; Long Multiply Instruction produces 64-bit result

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Move Instruction
MOV Rd,N
Rd : Destination Register N : Can be an Immediate Value or Source Register Example : MOV r7,r5

MVN Rd,N
Move into Rd Not of the 32-bit Value from Source

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Using Barrel Shifter


Enabling Shifting 32-bit operand in one of the source registers Left or Right by a specific number of positions within the cycle time of Instruction Basic Barrel Shifter Operations
Shift Left, Shift Right, Rotate Right

Facilitates Fast Multiply, Division and increases code Density Example : MOV r7,r5,LSL #2
Multiplies content of r5 by 4 and puts result in r7
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Using Barrel Shifter

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Arithmetic Instructions
Implements 32-bit Addition & Subtraction 3-Operand form Examples :
SUB r0,r1,r2 Subtract value stored in r2 from that of r1 & Store in r0 SUBS r1,r1,#1 Subtract 1 from r1 and store result in r1 and update Z & C Flags

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With Barrel Shifter


Use of Barrel Shifter with Arithmetic & Logical Instructions increases the set of possible available operations Example :
ADD r0,r1,r1 LSL #1 Register r1 is Shifted to the Left by 1, then it is added with R1 & the result (3 times r1) is stored in r0

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Multiply Instructions
Multiply Contents of a pair of Registers Long Multiply generates 64 bit result Examples :
MUL r0,r1,r2 Contents of r1 & r2 multiplied & put in r0 UMULL r0,r1,r2,r3 Unsigned Multiply with result stored in r0 & r1

Number of Cycles taken for the execution of Multiply Instruction depends upon Processor implementation
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Multiply & Accumulate


Result of Multiplication can be Accumulated with Content of another register Examples
MLA Rd,Rm,Rs,Rn Rd = (Rm*Rs) + Rn UMLAL Rdlo,Rdhi,Rm,Rs [RDhi,Rdlo] = [Rdhi,Rdlo] + (Rm*Rs)

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Logical Instructions
Bit Wise Logical operations on the two Source Registers
AND, OR, Ex-OR, Bit Clear

Example :
BIC r0,r1,r2 R2 contains a binary pattern where every binary 1 in r2 clears a corresponding bit location in r1 Useful in manipulating Status Flags & Interrupt Masks
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Compare Instructions
Enables Comparison of 32-bit values updates CPSR Flags but do not affect other Registers Examples :
CMP r0,r9 Flags set as a result of r0 r9
TEQ r0,r9 Flags set as a result r0 ex-or r9 TST r0,r9 Flags as a result of r0 & r9
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Summary
We have explained basics of ARM Architecture Understood Processor Modes We have looked at Core Data Path Discussed basic Data Processing Operations

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Thank You.
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