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ARM Architecture
ARM Architecture
Licensees
Intel Corporation Texas Instruments Analog Devices Inc. Atmel Corporation STMicroelectronics Cirrus Logic Altera Freescale Semiconductor Toshiba Samsung Electronics NXP Zilog Qualcomm Renesas Fujitsu Infineon Technologies, Sony Atheros Communications
ARM Architecture
ARM Architecture
ARM Architecture
Based on RISC Architecture with enhancements to meet requirements of Embedded applications
A Large Uniform Register File Load-Store Architecture, where data processing operates on register content only Uniform & fixed length Instructions 32-bit processor Instructions are 32-bit long Good Speed/Power Consumption Ratio High Code Density
ARM Architecture 6
ARM Architecture
Version 2
Includes 32-bit result multiply coprocessor
Version 3
32-bit Addressing
Version 4
Add Signed , Unsigned Half-word & Signed Byte Load & Store Instructions
Version 4T
16-bit Thumb - compressed form of Instructions
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Architecture Versions
Version 5T
Superset of 4T adding new Instructions
Version 5TE
Add Signal Processing Extension
ARM Architecture
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Early ARM architectures
5TE
5TEJ
System mode
ARM926EJ-S ARM1026EJ-S
4T
ARM9TDMI ARM940T
ARM1136EJ-S
ARM7TDMI
It is widely used across a range of application, notably in digital mobile telephones.
The THUMB 16-bit compressed instruction set. On-chip Debug support, enabling the processor to halt in response to a debug request. An enhanced Multiplier, with higher performance than its predecessors and yielding a full 64-bit result. 4 extra instructions are provided which performs 32 * 32 -> 64 multiplications and 32 * 32 + 64 -> 64 multiply and accumulate Embedded ICE hardware to give on-chip breakpoint and watch point support.
ARM Architecture
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ARM Architecture
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Increment/Decrement Logic can update the Register Content for Sequential access independent of ALU
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ARM Architecture
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Registers
General Purpose Registers hold either Data or Address All Registers are of 32-bits In User Mode 16 Data Registers and 2 Status Registers are Visible
Registers (2)
Depending upon the context, registers r13 & r14 can also be used as GPRs Any Instruction which use r0 can as well be used with anyother GPR (r1-r13)
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Register : r15
When the Processor is executing in ARM state
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28 27
24
23
16
15
N Z C V Q
I F T
mode
N Z C V
Set to 1 when result is negative Set to 1 when result is zero Set to 1 on carry or borrow generation and on shift operations Set to 1 if signed overflow occurs
ARM Architecture
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24
23
16
15
N Z C V Q
I F T
mode
I F
ARM Architecture
28 27
24
23
16
15
N Z C V Q
I F T
mode
Q Indicates occurrence of overflow and/or saturation M[4:0] 0b10000 0b10001 0b10010 0b10011 0b10111 0b11011 0b11111
ARM Architecture
Processor Modes
Processor Modes determine Which registers are Active Access Rights to CPSR Register itself Each Processor Mode is either Privileged : Full Read-Write access to the CPSR Non-Privileged : Only Read access to the Control Field of CPSR but Read-Write access to the Condition Flags
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Privileged : Abort, Fast Interrupt Request (FIQ), Interrupt Request (IRQ), Supervisor, System & Undefined
Non-Privileged : User User Mode is used for Programs and Applications
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Privileged Modes
Abort : When there is a failed attempt to access memory
Fast Interrupt Request (FIQ) & Interrupt Request : Correspond to Interrupt levels available on ARM Supervisor Mode : State after Reset and generally the mode in which OS kernel executes
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ARM Architecture
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Banked Registers
Register File contains in all 37 Registers
20 Registers are hidden from Program at different times These registers are called Banked Registers
Banked Registers are available only when the Processor is in a particular Mode
Processor Modes (other than System Mode) have a set of associated banked registers that are subset of 16 registers Maps one-to-one onto a User Mode register
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Register Banking
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SPSR
Each Privileged Mode (except System Mode) has Associated with it a Save Program Status Register, or SPSR This SPSR is used to save the state of CPSR when the Privileged Mode is entered in order that the user state can be fully restored when the user process is resumed
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Register Organization
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Mode Changing
Mode changes by writing directly to CPSR or by Hardware when the processor responds to Exception or Interrupt To return to User Mode a special return instruction is used that instructs the core to restore the original CPSR & Banked Registers
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bit 31
bit 0
bit 0
bit 31
Instructions
Instructions Process Data held in Registers and Access Memory with Load & Store instructions
Classes of Instructions
Data Processing Branch Instructions Load-Store Instructions Software Interrupt Instruction Program Status Register Instructions
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ARM Architecture
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Data Processing
Manipulate Data within Registers
MOVE Instructions Arithmetic Instructions Multiply Instructions Logical Instructions Comparison Instructions
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ARM Architecture
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Move Instruction
MOV Rd,N
Rd : Destination Register N : Can be an Immediate Value or Source Register Example : MOV r7,r5
MVN Rd,N
Move into Rd Not of the 32-bit Value from Source
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Facilitates Fast Multiply, Division and increases code Density Example : MOV r7,r5,LSL #2
Multiplies content of r5 by 4 and puts result in r7
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ARM Architecture
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Arithmetic Instructions
Implements 32-bit Addition & Subtraction 3-Operand form Examples :
SUB r0,r1,r2 Subtract value stored in r2 from that of r1 & Store in r0 SUBS r1,r1,#1 Subtract 1 from r1 and store result in r1 and update Z & C Flags
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ARM Architecture
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Multiply Instructions
Multiply Contents of a pair of Registers Long Multiply generates 64 bit result Examples :
MUL r0,r1,r2 Contents of r1 & r2 multiplied & put in r0 UMULL r0,r1,r2,r3 Unsigned Multiply with result stored in r0 & r1
Number of Cycles taken for the execution of Multiply Instruction depends upon Processor implementation
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ARM Architecture
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Logical Instructions
Bit Wise Logical operations on the two Source Registers
AND, OR, Ex-OR, Bit Clear
Example :
BIC r0,r1,r2 R2 contains a binary pattern where every binary 1 in r2 clears a corresponding bit location in r1 Useful in manipulating Status Flags & Interrupt Masks
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Compare Instructions
Enables Comparison of 32-bit values updates CPSR Flags but do not affect other Registers Examples :
CMP r0,r9 Flags set as a result of r0 r9
TEQ r0,r9 Flags set as a result r0 ex-or r9 TST r0,r9 Flags as a result of r0 & r9
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Summary
We have explained basics of ARM Architecture Understood Processor Modes We have looked at Core Data Path Discussed basic Data Processing Operations
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Thank You.
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