EE105 Fall 2007 Lecture 20, Slide 1 Prof.

Liu, UC Berkeley
Lecture 20
OUTLINE
Review of MOSFET Amplifiers
MOSFET Cascode Stage
MOSFET Current Mirror
Reading: Chapter 9
ANNOUNCEMENTS
HW#11 is due in 2 weeks, on 11/20.
Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium)
Midterm #2 (Thursday 11/15 in Sibley Auditorium):
Material of Lectures 11-18 (HW# 7-10; Chapters 6,9,11)
4 pgs of notes (double-sided, 8.511), calculator allowed
EE105 Fall 2007 Lecture 20, Slide 2 Prof. Liu, UC Berkeley
Review: MOSFET Amplifier Design
A MOSFET amplifier circuit should be designed to
1. ensure that the MOSFET operates in the saturation region,
2. allow the desired level of DC current to flow, and
3. couple to a small-signal input source and to an output load.
Proper DC biasing is required!
(DC analysis using large-signal MOSFET model)
Key amplifier parameters:
(AC analysis using small-signal MOSFET model)
Voltage gain A
v
v
out
/v
in

Input resistance R
in
resistance seen between the input node
and ground (with output terminal floating)
Output resistance R
out
resistance seen between the output
node and ground (with input terminal grounded)

EE105 Fall 2007 Lecture 20, Slide 3 Prof. Liu, UC Berkeley
MOSFET Models
The large-signal model is used to determine the DC
operating point (V
GS
, V
DS
, I
D
) of the MOSFET.




The small-signal model is used to determine how the
output responds to an input signal.
EE105 Fall 2007 Lecture 20, Slide 4 Prof. Liu, UC Berkeley
Comparison of Amplifier Topologies
Common Source
Large A
v
< 0
- degraded by R
S

Large R
in
determined by biasing
circuitry
R
out
~ R
D
r
o
decreases A
v
& R
out
but impedance seen
looking into the drain
can be boosted by
source degeneration

Common Gate
Large A
v
> 0
-degraded by R
S

Small R
in
- decreased by R
S
R
out
~ R
D
r
o
decreases A
v
& R
out
but impedance seen
looking into the drain
can be boosted by
source degeneration

Source Follower
0 < A
v
1
Large R
in
determined by
biasing circuitry
Small R
out
- decreased by R
S
r
o
decreases A
v
&
R
out
EE105 Fall 2007 Lecture 20, Slide 5 Prof. Liu, UC Berkeley
Common Source Stage
D out
in
S
m
D
G
v
R R
R R R
R
g
R
R R R
R R
A
=
=
+

+
=
2 1
2 1
2 1
||
1
||
||
0 =
0 =
( )
S O m O D out
R r g r R R + ~
EE105 Fall 2007 Lecture 20, Slide 6 Prof. Liu, UC Berkeley
Common Gate Stage
( )
( )
D m
G m S
m S
v
R g
R g R
g R
A
+
=
/ 1 ||
/ 1 ||
S
m
in
R
g
R
1
~
D out
R R =
( )
S O m O D out
R r g r R R + ~
0 =
0 =
EE105 Fall 2007 Lecture 20, Slide 7 Prof. Liu, UC Berkeley
Source Follower
S
m
S
v
R
g
R
A
+
=
1
G in
R R =
S o
m
out
G in
S O
m
S O
v
R r
g
R
R R
R r
g
R r
A
|| ||
1
||
1
||
=
=
+
=
0 =
0 =
S
m
out
R
g
R ||
1
=
EE105 Fall 2007 Lecture 20, Slide 8 Prof. Liu, UC Berkeley
CS Stage Example 1
M
1
is the amplifying device; M
2
and M
3
serve as the load.
1 2 3
3
1 2 3
3
1
|| || ||
1
|| || ||
1
O O O
m
out
O O O
m
m v
r r r
g
R
r r r
g
g A
=
|
|
.
|

\
|
=
Equivalent circuit for small-signal analysis,
showing resistances connected to the drain

EE105 Fall 2007 Lecture 20, Slide 9 Prof. Liu, UC Berkeley
CS Stage Example 2
M
1
is the amplifying device; M
3
serves as a source (degeneration)
resistance; M
2
serves as the load.
3
3 1
2
||
1 1
O
m m
O
v
r
g g
r
A
+
=
Equivalent circuit for small-signal analysis
0
1
=
EE105 Fall 2007 Lecture 20, Slide 10 Prof. Liu, UC Berkeley
CS Stage vs. CG Stage
With the input signal applied at different locations, these circuits
behave differently, although they are identical in other aspects.
S
m
O
v
R
g
r
A
+
=
2
1
1
| | { }
1 2 2 2 1
|| ) 1 (
O O S O m m v
r r R r g g A + + =
Common source amplifier Common gate amplifier
0
2
=
0
1
=
EE105 Fall 2007 Lecture 20, Slide 11 Prof. Liu, UC Berkeley
Composite Stage Example 1
By replacing M
1
and the current source with a Thevenin
equivalent circuit, and recognizing the right side as a CG stage,
the voltage gain can be easily obtained.
1 2
1 1
m m
D
v
g g
R
A
+
=
0
1
= 0
2
=
EE105 Fall 2007 Lecture 20, Slide 12 Prof. Liu, UC Berkeley
Composite Stage Example 2
This example shows that by probing different nodes in a circuit,
different output signals can be obtained.
V
out1
is a result of M
1
acting as a source follower, whereas V
out2

is a result of M
1
acting as a CS stage with degeneration.
2
2 1
4 3
3 2
||
1 1
|| ||
1
O
m m
O O
m
in
out
r
g g
r r
g
v
v
+
=
0
1
=
2
2 1
2
2 1
||
1 1
||
1
O
m m
O
m
in
out
r
g g
r
g
v
v
+
=
EE105 Fall 2007 Lecture 20, Slide 13 Prof. Liu, UC Berkeley
NMOS Cascode Stage
( )
2 1 1
1 2 1 1
1
O O m out
O O O m out
r r g R
r r r g R
~
+ + =
Unlike a BJT cascode, the output impedance is not limited by |.
EE105 Fall 2007 Lecture 20, Slide 14 Prof. Liu, UC Berkeley
PMOS Cascode Stage
( )
2 1 1
1 2 1 1
1
O O m out
O O O m out
r r g R
r r r g R
~
+ + =
EE105 Fall 2007 Lecture 20, Slide 15 Prof. Liu, UC Berkeley
Short-Circuit Transconductance
The short-circuit transconductance is a measure of the
strength of a circuit in converting an input voltage signal into
an output current signal:







The voltage gain of a linear circuit is
(R
out
is the output resistance of the circuit)
0 =

out
v
in
out
m
v
i
G
out m v
R G A =
EE105 Fall 2007 Lecture 20, Slide 16 Prof. Liu, UC Berkeley
Transconductance Example
1 m m
g G =
EE105 Fall 2007 Lecture 20, Slide 17 Prof. Liu, UC Berkeley
MOS Cascode Amplifier
| |
2 2 1 1
2 1 2 2 1
) 1 (
O m O m v
O O O m m v
out m v
r g r g A
r r r g g A
R G A
~
+ + ~
=
EE105 Fall 2007 Lecture 20, Slide 18 Prof. Liu, UC Berkeley
PMOS Cascode Current Source as Load
A large load impedance can be achieved by using a PMOS
cascode current source.
oP oN out
O O m oP
O O m oN
R R R
r r g R
r r g R
||
4 3 3
1 2 2
=
~
~
EE105 Fall 2007 Lecture 20, Slide 19 Prof. Liu, UC Berkeley
MOS Current Mirror
The motivation behind a current mirror is to duplicate a
(scaled version of the) golden current to other locations.
Current mirror concept Generation of required V
GS
Current Mirror Circuitry

( )
( )
REF
REF
copy
I
L W
L W
I
/
/
1
1
=
( )
1
1
/
2
TH
ox n
REF
X
V
L W C
I
V + =

( )
2
2
1
TH X
REF
ox n REF
V V
L
W
C I
|
.
|

\
|
= ( )
2
1
1
2
1
TH X ox n copy
V V
L
W
C I
|
.
|

\
|
=
EE105 Fall 2007 Lecture 20, Slide 20 Prof. Liu, UC Berkeley
MOS Current Mirror NOT!
This is not a current mirror, because the relationship between
V
X
and I
REF
is not clearly defined.









The only way to clearly define V
X
with I
REF
is to use a diode-
connected MOS since it provides square-law I-V relationship.
EE105 Fall 2007 Lecture 20, Slide 21 Prof. Liu, UC Berkeley
Example: Current Scaling
MOS current mirrors can be used to scale I
REF
up or down
I
1
= 0.2mA; I
2
= 0.5mA
: 0 =
EE105 Fall 2007 Lecture 20, Slide 22 Prof. Liu, UC Berkeley
Impact of Channel-Length Modulation
0 =
( ) ( ) | |
( ) | |
TH TH X
REF
ox n
sat D GS TH X
REF
ox n REF
V V V
L
W
C
V V V V
L
W
C I


+
|
.
|

\
|
=
+
|
.
|

\
|
=
1
2
1

1
2
1
2
,
2
( ) ( ) | |
( ) ( ) | |
TH GS DS TH X ox n
sat D DS TH X ox n copy
V V V V V
L
W
C
V V V V
L
W
C I
+ +
|
.
|

\
|
=
+
|
.
|

\
|
=
1
2
1
, 1
2
1
1
1
2
1

1
2
1


( )
( )
( ) ( )
( )
( )
|
|
.
|

\
|
+

+ =
+
+ +
=
TH
GS DS
REF
REF TH
TH GS DS
REF
REF
copy
V
V V
I
L W
L W
V
V V V
I
L W
L W
I

1
1
/
/
1
1
/
/
1 1 1 1
1
EE105 Fall 2007 Lecture 20, Slide 23 Prof. Liu, UC Berkeley
CMOS Current Mirror