EE 447 VLSI Design

Lecture 8: Circuit Families

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Outline

Pseudo-nMOS Logic Dynamic Logic Pass Transistor Logic

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Introduction

What makes a circuit fast? I = C dV/dt -> tpd (C/I) DV low capacitance high current B small swing A Logical effort is proportional to C/I 1 pMOS are the enemy! High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this
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4 4 Y 1

Pseudo-nMOS

In the old days, nMOS processes had no pMOS Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON Ratio issue Make pMOS about effective strength of pulldown network load
1.8 1.5 1.2 P = 24

P/2 Ids Vout 16/2 Vin

Vout 0.9 0.6 P = 14 0.3 0 0 0.3 0.6 0.9 Vin 1.2 1.5 1.8 P=4

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Pseudo-nMOS Gates

Design for unit current on output to compare with unit inverter. pMOS fights nMOS

Y inputs f

Inverter
gu gd gavg pu pd pavg = = = = = =

NAND2
gu g Y gd avg pu pd pavg = = = = = =

NOR2
gu gd gavg Y pu pd pavg = = = = = =

Y A

A B

EE 447 VLSI Design

Pseudo-nMOS Gates

Design for unit current on output to compare with unit inverter. pMOS fights nMOS

Y inputs f

Inverter
gu gd gavg pu pd pavg = = = = = =

NAND2
gu g Y gd avg 8/3 pu pd 8/3 pavg 2/3 A B = = = = = =

NOR2
gu gd gavg Y pu 4/3 pd pavg = = = = = =

2/3 Y A 4/3

2/3 A 4/3 B

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Pseudo-nMOS Gates

Design for unit current on output to compare with unit inverter. pMOS fights nMOS

Y inputs f

Inverter
gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = = =

NAND2
gu 2/3 g Y gd avg 8/3 pu pd 8/3 pavg = 8/3 = 8/9 = 16/9 = = =

NOR2
gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = = =

2/3 Y A 4/3

A B

2/3 A 4/3 B

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Pseudo-nMOS Gates

Design for unit current on output to compare with unit inverter. pMOS fights nMOS

Y inputs f

Inverter
gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9

NAND2
gu g Y gd avg 8/3 pu pd 8/3 pavg 2/3 A B = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9

NOR2
gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9

2/3 Y A 4/3

2/3 A 4/3 B

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Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS

G= F= P= N= D=

In1 Ink

1 Y 1 H

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Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS

G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N=2 4 2 H 8k 13 D = NF1/N + P = 3 9

In1 Ink

1 Y 1 H

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Pseudo-nMOS Power

Pseudo-nMOS draws power whenever Y = 0 Called static power P = IVDD A few mA / gate * 1M gates would be a problem This is why nMOS went extinct! Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use
en Y A B C

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Dynamic Logic

Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate
2 A 1 Static
Y

2/3 Y A 4/3 Y

1 Y 1

Pseudo-nMOS
Precharge

Dynamic
Evaluate Precharge

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The Foot

What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight.
Y A foot
footed unfooted

precharge transistor

Y inputs f

Y inputs f

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Logical Effort
Inverter NAND2
1 Y Y A 1 gd pd = = A B 2 2 gd pd = = A 1 1 Y B 1 gd pd = =

NOR2

unfooted

1 Y A 2 2 gd pd = = A B

1 Y 3 3 3 gd pd = = A 2 1 Y B 2 2 gd pd = =

footed

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Logical Effort
Inverter NAND2
1 Y Y A 1 gd pd = 1/3 = 2/3 A B 2 2 gd pd = 2/3 = 3/3 A 1 1 Y B 1 gd pd = 1/3 = 3/3

NOR2

unfooted

1 Y A 2 2 gd pd = 2/3 = 3/3 A B

1 Y 3 3 3 gd pd = 3/3 = 4/3 A 2 1 Y B 2 2 gd pd = 2/3 = 5/3

footed

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Monotonicity

Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 A 0 -> 1 1 -> 1 violates monotonicity during evaluation But not 1 -> 0
A Y Output should rise but does not Precharge Evaluate Precharge

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Monotonicity Woes

But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
A=1 A X X Y Precharge Evaluate Precharge

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Monotonicity Woes

But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
A=1 A X X X monotonically falls during evaluation Y Y should rise but cannot Precharge Evaluate Precharge

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Domino Gates

Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs
Precharge Evaluate Precharge

domino AND
W

W A B

X C

X Y Z

dynamic static NAND inverter

A B

W H C X

Y H Z = A B

X C

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Domino Optimizations

Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic
S0 D0 S1 D1 S2 D2 S3 D3 H S4 D4 S5 D5 S6 D6 S7 D7 Y

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Dual-Rail Domino

Domino only performs noninverting functions: AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs

sig_h 0 0 1 1

sig_l 0 1 0 1

Meaning Y_l Prechar inputs ged 0 1 EE 447 VLSI Design invalid

f f

Y_h

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Example: AND/NAND

Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B)

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Example: AND/NAND

Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements

Y_l = A*B A_l B_l

A_h B_h

Y_h = A*B

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Example: XOR/XNOR

Sometimes possible to share transistors

Y_l = A xnor B A_h A_l B_l

A_l B_h A_h

Y_h = A xor B

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Leakage

Dynamic node floats high during evaluation Transistors are leaky (IOFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation
weak keeper A 1 k 2 2 X H Y

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Charge Sharing

Dynamic gates suffer from charge sharing

A B=0 x Cx
x

Y CY

A Y

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Charge Sharing

Dynamic gates suffer from charge sharing

A B=0 x Cx
x

Y CY

A Y Charge sharing noise

Vx VY

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Charge Sharing

Dynamic gates suffer from charge sharing

A B=0 x Cx
x

Y CY

A Y Charge sharing noise

CY Vx VY VDD C x CY

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Secondary Precharge

Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance CY helps as well
Y A B x secondary precharge transistor

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Noise Sensitivity

Dynamic gates are very sensitive to noise Inputs: VIH Vtn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And more!

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Domino Summary

Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors

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Pass Transistor Circuits

Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: 2-input multiplexer Gates should be restoring
S A S B S
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S A Y B S S Y

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LEAP

LEAn integration with Pass transistors Get rid of pMOS transistors Use weak pMOS feedback to pull fully high Ratio constraint

S A S B L Y

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CPL

Complementary Pass-transistor Logic Dual-rail form of pass transistor logic Avoids need for ratioed feedback Optional cross-coupling for rail-to-rail swing
S A S B S A S B L Y L Y

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