Lecture 22

OUTLINE
The MOSFET (contd)
MOSFET scaling
Velocity saturation
Short channel effects

Reading: Pierret 19.1; Hu 7.1, 7.3
MOSFET Scaling
MOSFETs have been steadily miniaturized over time
1970s: ~ 10 m; today: ~25 nm
Benefits:
Increased device density --> lower cost per function
Improved circuit operating speed
I
Dsat
increases decreased effective R
gate and junction areas decrease decreased load C
faster charging/discharging
(i.e. t
d
is decreased)
Lecture 22, Slide 2 EE130/230A Fall 2013
MOSFET Scaling: Constant-Field Approach
MOSFET dimensions and the operating voltage (V
DD
) each are
scaled by the same factor k>1, so that the electric field
remains unchanged.
Lecture 22, Slide 3 EE130/230A Fall 2013
Constant-Field Scaling Benefits
Circuit speed
improves by k

Power dissipation
per function
is reduced by k
2
Lecture 22, Slide 4 EE130/230A Fall 2013
Since V
T
cannot be scaled down aggressively, the operating
voltage (V
DD
) has not been scaled down in proportion to the
MOSFET channel length:

Lecture 22, Slide 5 EE130/230A Fall 2013
Electric field intensity increases by a factor o>1
N
body
must be scaled up by o to suppress short-channel effects
Reliability and
power density
are issues

Lecture 22, Slide 6
MOSFET Scaling: Generalized Approach
EE130/230A Fall 2013
Velocity Saturation
Velocity saturation limits I
Dsat
in sub-micron MOSFETS

Simple model:





E
sat
is the electric field at velocity saturation:
sat
sat
v v
v
=
+
=
c
c
c
1

c
sat
sat
v 2
=
for c > c
sat
for c < c
sat

=
Si in holes for cm/s 10 6
Si in s on for electr cm/s 10 8
6
6
sat
v
Lecture 22, Slide 7 EE130/230A Fall 2013
MOSFET I-V with Velocity Saturation
L
V
V V
m
V V C
L
W
I
sat
DS
DS DS T GS eff oxe
D
c

+
|
.
|

\
|

=
1
2
L
V
I channel long
I
sat
DS
D
D
c
+

=
1
In the linear region:
Lecture 22, Slide 8 EE130/230A Fall 2013
Drain Saturation Voltage, V
Dsat
If c
sat
L >> V
GS
-V
T
then the MOSFET is considered
long-channel. This condition can be satisfied when
L is large, or
V
GS
is close to V
T
L V V
m
V
sat T GS Dsat
c
1 1
+

c
sat
sat
v 2
=
Lecture 22, Slide 9 EE130/230A Fall 2013
Example: Drain Saturation Voltage
Question: For V
GS
= 1.8 V, find V
Dsat
for an NMOSFET
with T
oxe
= 3 nm, V
T
= 0.25 V, and W
T
= 45 nm, if L =
(a) 10 m, (b) 1 m, (c) 0.1 m (d) 0.05 m


Solution: From V
GS
, V
T
and T
oxe
,
eff
is 200 cm
2
V
-1
s
-1
.

E
sat
= 2v
sat
/
eff
= 8 10
4
V/cm
m = 1 + 3T
oxe
/W
T
= 1.2

1
1

|
|
.
|

\
|
+

=
L V V
m
V
sat T GS
Dsat
c
Lecture 22, Slide 10 EE130/230A Fall 2013
(a) L = 10 m: V
Dsat
= (1/1.3V + 1/80V)
-1
= 1.3 V

(b) L = 1 m: V
Dsat
= (1/1.3V + 1/8V)
-1
= 1.1 V

(c) L = 0.1 m: V
Dsat
= (1/1.3V + 1/.8V)
-1
= 0.5 V

(d) L = 0.05 m: V
Dsat
= (1/1.3V + 1/.4V)
-1
= 0.3 V
Lecture 22, Slide 11 EE130/230A Fall 2013
I
Dsat
with Velocity Saturation
Substituting V
Dsat
for V
DS
in the linear-region I
D
equation gives
For very short L:
I
Dsat
is proportional to V
GS
V
T
rather than (V
GS
V
T
)
2
I
Dsat
is not dependent on L

( )
L m
V V
I channel long
L m
V V
V V C
mL
W
I
sat
T GS
Dsat
sat
T GS
T GS eff oxe
Dsat
c c

=
1 1
2
2
( ) m V V L
T GS sat
/ << c
( ) ( )
T GS oxe sat T GS eff oxe sat Dsat
V V C Wv V V C
W
I = = c
2
Lecture 22, Slide 12 EE130/230A Fall 2013
Short- vs. Long-Channel NMOSFET
Short-channel NMOSFET:
I
Dsat
is proportional to V
GS
-V
Tn
rather than (V
GS
-V
Tn
)
2
V
Dsat
is lower than for long-channel MOSFET
Channel-length modulation is apparent
Lecture 22, Slide 13 EE130/230A Fall 2013
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-23
Velocity Overshoot
When L is comparable to or less than the mean free
path, some of the electrons travel through the channel
without experiencing a single scattering event
projectile-like motion (ballistic transport)
The average velocity of carriers exceeds v
sat
e.g. 35% for L = 0.12 m NMOSFET

Effectively, v
sat
and c
sat
increase when L is very small
Lecture 22, Slide 14 EE130/230A Fall 2013
The Short Channel Effect (SCE)
|V
T
| decreases with L
Effect is exacerbated by
high values of |V
DS
|



This effect is undesirable (i.e. we want to minimize it!)
because circuit designers would like V
T
to be invariant
with transistor dimensions and bias condition
V
T
roll-off
Lecture 22, Slide 15 EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.3
Qualitative Explanation of SCE
Before an inversion layer forms beneath the gate, the
surface of the Si underneath the gate must be
depleted (to a depth W
T
)
The source & drain pn junctions assist in depleting the
Si underneath the gate
Portions of the depletion charge in the channel region are
balanced by charge in S/D regions, rather than by charge on
the gate
Less gate charge is required to invert the semiconductor
surface (i.e. |V
T
| decreases)
Lecture 22, Slide 16 EE130/230A Fall 2013
depletion
charge
supported
by gate
(simplified
analysis)
n
+
n
+
V
G
p
depletion region
Large L:
S D
Small L:
D S
Depletion charge
supported by S/D
Depletion charge
supported by S/D
The smaller L is, the greater the percentage of
depletion charge balanced by the S/D pn junctions:
r
j
Lecture 22, Slide 17 EE130/230A Fall 2013
First-Order Analysis of SCE
(
(

+ =
'
1
2
1 2
j
T
j
r
W
r L L
L
L L
2
1
'
+

W
T
Lecture 22, Slide 18
The gate supports the depletion charge in the trapezoidal region.
This is smaller than the rectangular depletion region underneath
the gate, by the factor




This is the factor by which the depletion charge Q
dep
is reduced
from the ideal
One can deduce from simple geometric analysis that
EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.4
V
T
Roll-Off: First-Order Model
|
|
.
|

\
|
+

= A

1
2
1
) (
j
T
j
oxe
T A
T channel long T T
r
W
L
r
C
W qN
V V V
Minimize AV
T
by
reducing T
oxe
reducing r
j
increasing N
A

(trade-offs: degraded
eff
, m)
MOSFET vertical dimensions should be
scaled along with horizontal dimensions!
Lecture 22, Slide 19 EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.4
Drain Induced Barrier Lowering (DIBL)
As the source and drain get closer, they become electrostatically
coupled, so that the drain bias can affect the potential barrier to
carrier diffusion at the source junction.
V
T
decreases (i.e. OFF state leakage current increases)
Lecture 22, Slide 20 EE130/230A Fall 2013
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7-5
Punchthrough
A large drain bias can cause the drain-junction depletion region to
merge with the source-junction depletion region, forming a sub-
surface path for current conduction.
I
Dsat
increases rapidly with V
DS
This can be mitigated by doping the semiconductor more heavily
in the sub-surface region, i.e. using a retrograde doping profile.
Lecture 22, Slide 21 EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.6