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Tutorial 11
The Microprocessor and its Architecture

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Objectives

Revision on lecture note(CPU Architecture) Intel x86

By Ivan Leung

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CPU

What is CPU?

one central unit that executes program instructions communicates with and controls the operation of other subsystems within the computer its main function to fetch and execute instructions

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CPU
Floppy Memory

Harddisk

CPU

Monitor

Mouse

Keyboard

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CPU Fundamental

As you know, fetching and execution are broken down into smaller steps(e.g. movement between registers, addition by using ALU, etc) Each of these smaller steps is a machine code, i.e. an assembly instruction Assembly program will be assembled to machine instructions and then put in the main memory (You should know that already, Right?)

By Ivan Leung

Tutorial 11
CPU Fundamental

Depends on the machine instruction, the CPU will generate a set of control signals to control other subsystem (You also known that) CPU bus(What is bus?)

The bus is internal to the CPU connected the components in the CPU (e.g. ALU, GPR, MAR, MDR, PC, )

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CPU
CPU with Single-bus
To main memory
Memory bus

Memory Function Completion: indicates the operation in memory is completed CPU internal bus
Control MFC Signals READ .... PC Address lines Data lines Instruction Decoder

CPU bus

From control unit

MAR

MDR

IR

Y Add Sub : : XOR

ALU Control lines

ALU Carry-in Z

R0 : : R(n-1)

TEMP

Y,Z and TEMP are registers. That are transparent to programmers. CPU will use it by itself.

From control unit By Ivan Leung 7

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Example of Bus organization

Fetch a Word from MM

Assume the address of the memory location to be accessed is in R1 and the memory data are to be loaded into R2
1. 2. 3. 4. MAR <= [R1] Read (control to memory) Wait for MFC from memory R2 <= [MDR] CPU idle 1. 2. 3. MAR <= [R1] MDR <= [R2], Write signal to control Wait for MFC from memory By Ivan Leung 8

Write a Word to MM

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Control signals

To MM:

Read, Write, Reset, etc Riin input data to Ri from CPU bus if 1 Riout output data in Ri to CPU bus if 1; 0: bus is used by others reset, etc Add, Sub, Mul, Div, etc
By Ivan Leung 9

To Registers:

To ALU:

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Example of Control Signals
R(i-1) in

Add data in R1 and R2 registers and put the result to R3

1. R1out,Yin

R(i-1)

R(i-1) out Yin

Yout

2.
3.

R2out, Add, Zin

Zout, R3in
A

B ALU

Electronic switch: In control 1 will get input else will not Out control 1 will output the data else 0 will not By Ivan Leung

Zin

Zout

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1-bit register with Switch
1 bit line of common bus S Q Z/1/0

Z means the tri-state is in high impedance mode

Control to SR latch
R

electronic switch

Zin

Zout

tri-state Open-collector (bipolar) NAND gate

SR latch (God! What is it?) By Ivan Leung

Zout

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Control Sequence

ADD A,R1
1. PCout,MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout,PCin, WMFC MDRout,IRin IRout,MARin, Read R1out,Yin, WMFC MDRout,Add,Zin Zout,R1in,End Load [PC] into MAR; Send Read request to the memory; Reset Y to all 0s Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z Load [Z] to PC wait for memory to complete Got data in MDR from MM and load it to IR Load address of A to MAR Send Read request to the memory Load [R1] to Y and further to ALU wait for memory to complete Got data in MDR from MM and load it to ALU, add it to [Y], and write result to Z Load [Z] to R1 By Ivan Leung 12

Fetch Execution

2. 3. 4. 5. 6. 7.

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Control Sequence

BRN(conditional/unconditional)
1. PCout,MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout,PCin, WMFC MDRout,IRin PCout, Yin IRout, Add, Zin Zout,PCin,End Load [PC] into MAR; Send Read request to the memory; Reset Y to all 0s Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z Load [Z] to PC wait for memory to complete Got data in MDR from MM and load it to IR Load branch address to Y and further to ALU Load [IR] to ALU and add it to [Y], put the result to Z Load [Z] to PC

2. 3. 4. 5. 6.

For step 4, if not satisfy branch condition, then End branch address = [PC] + Offset
By Ivan Leung 13

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CPU with 3 internal buses

B Instruction Decoder IR

required significantly fewer control steps

ADD R1,R2,R3 (one clock cycle)

execution phase to be performed in one clock cycle Y is not required because ALU can take two inputs from two registers from two data buses Z is not required because ALU can write the result to the destination register by 3rd bus performs register-to-register operations in a single clock cycle
Data lines

PC

Register File

TEMP

ALU

MDR

MAR Address lines

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Memory bus

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CPU Architecture
Instruction Unit (IR) Integer unit Processor Floating-point Processor

Instruction Cache

Data Cache

Bus Interface

CPU
System Bus

Main Memory

Input/ Output

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Control Signal

But how to generate the control signals as the control sequence discussed before?

By microprogramming Using a sequence of microinstructions to generates a sequence of control signals

What is microprogramming?

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Microprogramming

A control word(CW) is a word whose individual bits represent the various control signals Each CW represents a set of control signals in one step of control sequence of an instruction, which is called microinstruction A sequence of CWs, which is referring to the control sequence of a machine instruction, is called microroutine Microprogram memory contains the microroutine of all instructions Depends on [IR], a starting address of corresponding microroutine is given to microprogram counter MicroPC will be incremented and then a sequence of CWs will be given out

IR

Starting address generator

Clock

PC

Microprogram memory

CW

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Hand-shaking with Memory

In the control sequence, there are steps that have to wait for MFC from memory. A signal WMFC is used.
Read J Q MR

Q To main memory

Write J Q

MW

Q MFC RUN Control Setup Counter

WMFC Clk

RUN 0 iff

MFC MR WAIT
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Tutorial 11
Hand-shaking with Memory

Control step Clk

i+1

i+2

Why MR?

if

// Read // // MR // WMFC

RUN WAIT MFC But, if it starts at (i+1)-th pulse, RUN 1 1 0 1 However, after the drop of (i+1)-th pulse and before the raise of (i+2)-th pulse, RUN 1 0 1 0 It is wrong!

MFC // RUN // t1 t2 t3 t4 t5

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80x86

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8086 (Review)

16-bit processor with 20-bit address bus Direct mode addressing with memory space of 1MByte 14 words by 16-bit register set (You should be familiar with them) Byte addressable For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location

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8086 (Review)

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8086

Why there is no Program Counter(PC)?

How stack works?

How to indicate the next instruction to be executed?

How CALL works?

What is the function of SP? What is the starting position of SP? How to jump to other procedure? How to return(RET) to previous procedure?
By Ivan Leung 23