01 ASIC Design Flow

ASIC Design Flow
TS. Hoang Trang ThS. Pham Dang Lam
12/2012
ASIC Design Subject
Idea
12/2012
ASIC Design Subject
Idea
Hardware Develop
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ASIC Design Subject
Idea
Third party
Hardware Develop
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ASIC Design Subject
Idea
Third party
Hardware Develop
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ASIC Design Subject

Factory
Idea
Layout
Third party
Hardware Develop
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ASIC Design Subject

Physical Chip Factory
Idea
Layout
Third party
Hardware Develop
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ASIC Design Subject

Physical Chip Factory
Idea
Layout
Third party
Hardware Develop
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ASIC Design Subject

Design Methodology
Fully Custom
Semi Custom
Standard Cells
Gate Arrays
Programmable Logic
FPGA
PLD
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ASIC Design Subject

ASIC Design Flow (Application-specific integrated circuit)
Design Methodology
Fully Custom
Semi Custom
Standard Cells
Gate Arrays
Programmable Logic
FPGA Design Flow (Field Programmable Gate Array)
FPGA
PLD
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ASIC Design Subject

Standard Cell Base Full Custom Gate Array PLD
Design a chip from scratch Engineer design some or all the logic cells, circuits, and the chip layout specifically for a full-custom IC Advantages: Complete flexibility, high degree of optimization performance ad area Disadvantages: Large amount of design effort, expensive
Use predesigned, pretested and pre_characterized logic cells from the standardscell library as building blocks.
The chip layout is customized Advantages: Save design time and money, reduce risk compared to full-custom design Disadvantages: Still incurs high nonerecurring-engineering (NRE) cost and long manufacture time
Parts of the chip are prefabricated, and other parts are custom fabricated for particular customers circuit. Idential base cells are pre-fabricated in the form of a 2-D array on a gatearray (this partially finished chip is called gate-array template). This wires between the transistors inside the cells and between the cells are custom fabricated for each customer Custom mask are made for the wiring only
A PLD is a generalpurpose chip for implementing logic circuitry. Transistors and wires are already prefebricated on a PLD Logic cells and interconnect can be programmed by end-user to implement specific circuitry No need to create custom masks for each customer
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ASIC Design Subject

Hardware Development Activities
Front end Design

ASIC Design Flow Back end Design Mask Production
Design
GDS
Manufacturing
Fabrication/Test Packaging/Test Shipping
Front end Process (Wafer Process) Back end Process
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ASIC Design Subject

Discrete Device Semiconductor Device Integrated Device Hardware
Led BJT Diode FET Digital Analog Mix Signal
Product
Board, Hardware Flatform
Compiler, OS Software Device driver Middleware
Develop & Evaluate Design Kit
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ASIC Design Subject

Discrete Device Semiconductor Device Integrated Device Hardware
Led BJT Diode FET Digital Analog Mix Signal
Product
Board, Hardware Flatform
Compiler, OS Software Device driver Middleware
Develop & Evaluate Design Kit
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ASIC Design Flow

Cell Base & Custom Design Flow Concepts Custom Design Flow
Cell Base Design Flow

ASIC vs. FPGA Design Flow
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ASIC Design Flow


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Cell Base & Custom Design Flow Concepts

ASIC Design Products
Products for Cell Base Design Flow
Products for Custom Design Flow
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ASIC Design Products
Products for Cell Base Design Flow MCU: I2C, DMAC, SBI, SCI, PCI, UART, TIMER, CAN, etc. DSP: Digital Filter, router, etc.
Products for Custom Design Flow Analog Device: ADC, PLL, Amplier, etc. Memory: ROM, RAM, etc MisSignal: RFID, etc
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Custom Design Flow
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Custom Design Flow
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Custom Design Flow
CMOS Level
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Custom Design Flow
CMOS Level
Symbol Level
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Custom Design Flow
ADC IP
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Custom Design Flow
ADC IP
Build Library from the scratch
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Cell BaseDesign Flow
y = !(x1 & x2);
y = !(x1 I x2);
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y = !(x1 & x2);
RTL Level
y = !(x1 I x2);
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y = !(x1 & x2);
matching
y = !(x1 I x2);
matching
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UART IP y = !(x1 & x2);

matching
y = !(x1 I x2);
matching
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UART IP y = !(x1 & x2);

matching
Ready Library
y = !(x1 I x2);
matching
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ASIC Design Flows
Custom Design Flow
Design a chip from scratch Engineer design some or all the logic cells, circuits, and the chip layout specifically for a full-custom IC Advantages: Complete flexibility, high degree of optimization performance ad area Disadvantages: Large amount of design effort, expensive
Use predesigned, pretested and pre_characterized logic cells from the standards-cell library as building blocks. The chip layout is customized Advantages: Save design time and money, reduce risk compared to fullcustom design Disadvantages: Still incurs high nonerecurring-engineering (NRE) cost and long manufacture time
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comparision Integration Density Speech Chip Scale Support Tools Time to market Risk reduction X X X X Cell Base Design Custom Design X X
http://www.ami.ac.uk/courses/ami4407_dicdes/u03/#3.2 http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro.pdf http://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf
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ASIC Design Flow


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Custom Design Flow

Design flow Support Tools Output
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic
Composer
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic NG
Composer
Netlist extraction
Composer
<file>.cdl, <file>.net
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic NG
Composer
Netlist extraction Pre_Layout Verification
Composer
HSpice
<file>.wf, <file>.tr
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic NG
Composer
Netlist extraction Pre_Layout Verification Layout
Composer
HSpice
Virtuoso
<file>.gds
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic NG
Composer
Composer
HSpice
Virtuoso NG
<file>.gds <file>.db (DRC) <file>.svdb(LVS)
Layout Verification
Calibre
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DRC: Design Rule Check LVS: Layout Versus Schematic
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Custom Design Flow

Specifications
<file>.docx/xls/ppt
Schematic NG
Composer
Composer
HSpice
Virtuoso NG
<file>.gds <file>.db (DRC) <file>.svdb(LVS)
Layout Verification
Calibre
RC_extraction Pos_Layout Verification Report file <file>.lib/.db
Spectre Simulator Pritime
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DRC: Design Rule Check LVS: Layout Versus Schematic
40
ASIC Design Flow


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Design flow Support Tools (Languages) Output
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Specifications
<file>.docx/xls/ppt
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Specifications
<file>.docx/xls/ppt
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Specifications
<file>.docx/xls/ppt
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Specifications System Level Design G++ (C++ with Sysem C class)
<file>.docx/xls/ppt
Flatform / Model
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Specifications System Level Design RTL Design G++ (C++ with Sysem C class) VI, NotePath++ (Verilog/VHDL)
<file>.docx/xls/ppt
Flatform / Model
<file>.v
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Specifications System Level Design RTL Design NG G++ (C++ with Sysem C class) VI, NotePath++ (Verilog/VHDL) VCS/ModelSim, etc(Verilog/ VHDL)
<file>.docx/xls/ppt
Flatform / Model
<file>.v Report file, wave form
RTL Verification
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Specifications System Level Design RTL Design NG NG G++ (C++ with Sysem C class) VI, NotePath++ (Verilog/VHDL) VCS/ModelSim, etc(Verilog/ VHDL) DC compiler
<file>.docx/xls/ppt
Flatform / Model
<file>.v Report file, wave form <file>.v (netlist), <file>.sdf, Reports
RTL Verification
Synthesis
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Specifications System Level Design RTL Design NG NG G++ (C++ with Sysem C class) VI, NotePath++ (Verilog/VHDL) VCS/ModelSim, etc(Verilog/ VHDL) DC compiler NG Netlist Verification Formality
<file>.docx/xls/ppt
Flatform / Model
<file>.v Report file, wave form <file>.v (netlist), <file>.sdf, Reports Report file
RTL Verification
Synthesis
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<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
DFT
FastScan/Tmax/
Report file, Netlist
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<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
DFT
FastScan/Tmax/
STA
Prime Time
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<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
DFT
FastScan/Tmax/
STA
Prime Time
Place&Route
ICC compiler
<file>.gds
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<file>.docx/xls/ppt
Flatform / Model
Front End
RTL Verification
Synthesis
DFT
FastScan/Tmax/
Back End
STA
Prime Time
Place&Route
ICC compiler
<file>.gds
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Specifications
<file>.docx/xls/ppt
Design the one bit adder: + Three inputs (A, B, Cin) + Two output (S, Cout)
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Specifications System Level Design G++ (C++ with Sysem C class)
<file>.docx/xls/ppt
Flatform / Models
Flatform/Model concepts
TLM class
C++
Methods in SystemC class
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Specifications System Level Design RTL Design VI, NotePath++ (Verilog/VHDL)
<file>.docx/xls/ppt
<file>.v
Verilog/VHDL language
Coding style
Design vs. Model
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Specifications System Level Design RTL Design VI, NotePath++ (Verilog/VHDL) VCS/ModelSim, etc(Verilog/ VHDL)
<file>.docx/xls/ppt
<file>.v Report file, wave form
RTL Verification
VCS tool
Check list
Verification Environment
58
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Specifications System Level Design RTL Design NG NG VI, NotePath++ (Verilog/VHDL) VCS/ModelSim, etc(Verilog/ VHDL) DC compiler
<file>.docx/xls/ppt
<file>.v Report file, wave form <file>.v (netlist), <file>.sdf, Reports
RTL Verification
Synthesis
Timing analysis
Tool commands
Report analysis
59
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<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
Tool commands
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Report analysis
60

<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
DFT
FastScan/Tmax/
MBIST
LBIST
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<file>.docx/xls/ppt
Flatform / Model
RTL Verification
Synthesis
DFT
FastScan/Tmax/
STA
Prime Time
Timing analysis
Tool commands 12/2012
Report analysis
62

DFT
FastScan/Tmax/
STA
Prime Time
Place&Route
ICC compiler
<file>.gds
Timing/Area analysis
Library Using
Tool Commands
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ASIC Design Flow


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ASIC
1986: Synopsys 1987: TSMC 1988: Cadence
FPGA
1983: Altera 1984: Xilinx
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Appendix
ASSP : Application Specific Standard Product (DSP, Mircro Processor) ASCP: Application Specific Custom Product GDS: Graphic Data System
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Appendix
Language Design Level Transaction Transaction RTL RTL Gate Simula Synthesiz Explicit tion eable Hardware Resource Yes Yes Yes Yes Yes No Yes* Yes* Yes* Yes No No Yes* Yes* Yes Elapsed Time No Yes Yes Yes Yes Sequence
C++ SystemC VHDL Verilog Verilog/VHD L Netlist
Yes Yes Yes Yes Yes
Yes*: Base on the constraints to be able or not

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Q&A
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Reference
1. Cell Characterization Concepts slide - SIVACO company 2. Henrik Eriksson and Per Larsson-Edefors, Tomas Henriksson and Christer Svensson, Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study 3. TSMC 65nm CLN65LP HVT Process 1.2-Volt 12-Track AdvantageTM v2.1Standard Cell Library Databook 4. http://www.ami.ac.uk/courses/ami4407_dicdes/u03/ 5. http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro .pdf 6. http://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf
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Question
Q1/ Why Static Timing Analysis step is only done after Place and Route step in FPGA design flow ? Q2/ In FPGA and ASIC design flows, which s performances such as area and timing are better? Q3/ Why is Time to Market of FPGA design flow faster ?
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Question
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01 ASIC Design Flow

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01 ASIC Design Flow

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ASIC Design Flow

TS. Hoang Trang ThS. Pham Dang Lam

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

ASIC Design Subject

FPGA Design Flow (Field Programmable Gate Array)

ASIC Design Subject

ASIC Design Subject

Front end Design

Fabrication/Test Packaging/Test Shipping

Front end Process (Wafer Process) Back end Process

ASIC Design Subject

Led BJT Diode FET Digital Analog Mix Signal

Board, Hardware Flatform

Compiler, OS Software Device driver Middleware

Develop & Evaluate Design Kit

ASIC Design Subject

Led BJT Diode FET Digital Analog Mix Signal

Board, Hardware Flatform

Compiler, OS Software Device driver Middleware

Develop & Evaluate Design Kit

ASIC Design Flow

Cell Base Design Flow

ASIC Design Flow

Cell Base Design Flow

Cell Base & Custom Design Flow Concepts

Products for Cell Base Design Flow

Products for Custom Design Flow

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Cell Base & Custom Design Flow Concepts

Build Library from the scratch

Cell Base & Custom Design Flow Concepts

y = !(x1 & x2);

Cell Base & Custom Design Flow Concepts

y = !(x1 & x2);

Cell Base & Custom Design Flow Concepts

y = !(x1 & x2);

Cell Base & Custom Design Flow Concepts

UART IP y = !(x1 & x2);

Cell Base & Custom Design Flow Concepts

UART IP y = !(x1 & x2);

Cell Base & Custom Design Flow Concepts

Cell Base Design Flow

Custom Design Flow

Cell Base & Custom Design Flow Concepts

http://www.ami.ac.uk/courses/ami4407_dicdes/u03/#3.2 http://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/1_dintro.pdf http://www.ece.ucdavis.edu/~bbaas/116/notes/Handout.std.cell.design.pdf

ASIC Design Flow

Cell Base Design Flow

Custom Design Flow

Custom Design Flow

Custom Design Flow

Custom Design Flow

Custom Design Flow