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PARALLEL TO
PROCESSO SERIAL DEVICE
R MODEM
(PARALLEL (SERIAL)
SERIAL TO
)
PARALLEL
CLK
DATA
ASYNCHRONOUS
TRANSMISSION
Start and stop bits
SYNCHRONOUS
• BLOCK OF DATA TRANSMITTED ALONG
WITH SYNC INFORMATION
• HIGH SPEED TRANSMISSION
ASYNCHRONOUS
•CHARACTER CARRIES INFORMATION WITH
START AND STOP BITS
•WHEN NO DATA IS TRANSMITTED RECEIVER
STAYS AT LOGIC 1 CALLED MARK ; LOGIC 0
CALLED SPACE
•TRANSMISSION STARTS WITH ONE START
BIT AND ONE OR MORE STOP BITS . THIS IS
FRAMING
Serial Interfaces: RS-232
BUT
USUSALLY YEP…. THATS
LOGIC 1 RIGHT…..
+12V HERE WE USE
LOGIC 0- NEGATIVE TRUE
12V LOGIC
????!!!!!!
• TO MAKE RS 232 COMPATIBLE WITH TTL LOGIC ,
• VOLTAGE TRANSLATORS CALLED LINE DRIVERS
& LINE RECEIVERS ARE USED
RS232 pins
SIGNA
LS OF
RS232
11 bits required to send a single character (10 if
one stop bits are used)
Bit rate (bits/sec): actual rate at which bits are
transmitted
Baud rate: rate at which the signalling
elements, used to represent bits, are transmitted
TX RX
DTE 2 2
MICRO RX TX
DCE
COMPUT3 3
ER GND
MODEM
7 7
TX TX
2 2
DTE 3
RX RX DTE
3
GND
7 7
Typical System Connections
7 7
SERIAL INTERFACES : 8251A
USART
The functions and requirement for SERIAL I/O are,
Input port & Output port for interfacing
DATA TX MPU converts parallel to serial
DATA RX MPU converts serial to parallel
Synchronization between MPU and slow peripheral
GND GROUND
SIX THREE BUFFER
INPUT REGISTERS
SIGNALS • STATUS REG.
•CONTROL REG
•DATA REG.
RESET – Reset
LOGIC 1 forces 8251 to RESET
and enters into idle mode
CLK - clock
REFERS TO SYSTEM CLOCK
Necessary for communication with the
processor
8251 mode register- MODE WORD
PARITY CONTROL
X0 – NO PARITY
01 – ODD PARITY
11 – EVEN PARITY
Command Register
Status Register
MPU INFORMS 8251 – MODE, BAUD, STOP
BITS, PARITY
CONTROL WORDS TO BE LOADED FROM MPU
TO 8251
OPERATION FLOW