Arithmetic logic unit

CREATING AN ARITHMETIC LOGIC UNIT IN MICROWIND

Objectives
To complete a design of an arithmetic logic unit using the schematic provided. To design a high speed and low power consumption arithmetic logic unit. To observe and differentiate the output of the some vlsi layout techniques and how will they affect the final device.

Method
Using our previous works, we will choose the best circuits that will satisfy our desired output behavior. These layouts must optimize the power consumption as well as its speed without sacrificing too much on the area.

DESIGN LAYOUT AND ANALYSIS

We are already given the schematic of an ALU that we will follow as well as its Functionality Table.
less A
D0 D1 D2 D3 A B ~G

U6
Y ~W

Result

MUX_4TO1

op opb

U5
D0 D1 Y ~W A B CIN

U7
SUM CARRY

set Cout

A ~G

MUX_2TO1

FULL_ADDER

binv

Cin

Functionality Table
Operation
a&b
a or b a+b (addition)

Op[1:0] MUX 4
00
01 10

Binv MUX 2
0
0 0 1 ;Cinmust also be 1 1 ;Cinmust also be1

a-b (subtraction) a+~b+1 10 Less 11

List of Components
Inverter

And gate
Or gate

2 to 1 MUX
Full adder

4 to 1 MUX

Inverter

We used Dsch3 program to implement transistor layout of our components.

Using our previous works. We choose the inverter with a PMOS width of 8 lambdas and a NMOS width of 4 lambdas.

Inverter Layout; DRC check passed We then use this layout as a default for the worst case sizing of the AND gate and the OR gate.

Inverter Analysis:

Functionality test passed. Output is smooth and no glitches were found. There is a 4ps delay on low-to-high transition and 2ps delay on high-tolow transition. Which is considerably fast.

Inverter Analysis:

Power consumption is reduced, better than our previous designs. Spikes occurs when both transistors but with minimum power consumption.

Inverter Analysis:

The circuit is almost symmetric. Vdd/2 = 0.598V, .002V away from .6 to achieve perfect symmetry.

AND gate

Using worst case sizing ratio, we base the size of Pmos and Nmos on the ratio found in our inverter.

This design reduces the capacitance of the whole design by minimizing the spacing between each of the transistors.

AND gate analysis:

AND gate analysis:

Functionality test passed. Output is smooth and no glitches were found. There is a8ps delay on low-to-high transition and 4ps delay on high-to-low transition. Fastest Design in comparison with our previous layouts.

A spike will occur at the output on device initialization.

AND gate analysis:

AND gate analysis:

Power consumption is not that low, because in the increase in size due to the worst case ratio.
But spike when both Pmos and Nmos are on, is reduced compared to our previous layouts which doesnt use the ratio.

Idd Max = 0.454mA; IddAvr=0.002mA

AND gate analysis:

Vdd/2 = 0.558V , .042V away from .6 to achieve perfect symmetry

OR gate

Using worst case sizing ratio, we base the size of Pmos and Nmos on the ratio found in our inverter.

Or gate analysis

Or gate analysis
Functionality test passed. Output is almost smoot.

Spike is detected at initialization.

There is a 10ps delay on low-to-high transition and 8ps delay on high-to-low transition. Still faster than our design not using the Worst case ratio.

Or gate analysis

Or gate analysis

Power consumption is considerably lower than our previous designs.

A spike is detected at initialization Reduced spikes cause by having both Pmos and Nmos on at transistors transitions. Iddmax=.124mA

Or gate analysis

Vdd/2 is almost perfectly symmetrical. Vdd/2=.590V, .10V away from perfect symmetry.

2-1 Multiplexer
U5
D0 D1 A ~G Y ~W

MUX_2TO1

In choosing our 2-1 MUX we had chosen the one implemented using transmission gates. We found that using transmission gates. We can optimize power consumption and speed, and it it even requires less transistors than the other designs.

2-1 Multiplexer

Dsch3 implementation of the 2-1 multiplexer using transmission gates

2-1 Multiplexer

2 to 1 MUX Layout using Microwind DRC check passed

2 to 1 Mux analysis

2 to 1 Mux analysis
Functionality test passed. The circuit doesnt need to initialize after first power on. It will immediately display the right output. Significantly fast compared to the previous design with only 6 picoseconds delays.Output is smooth and no glitches were found.

2 to 1 Mux analysis

2 to 1 Mux analysis
Current spikes only occur when the inverter signal changes output. Significantly reducing power consumption. Reduced instances that both PMOS and NMOS are on.

Idd Max = 0.121mA

IddAvr = 0.000 mA

2 to 1 Mux analysis

Perfectly symmetric design Threshold attenuation eliminated because of the CMOS transmission gates

4-1 Multiplexer
U6
D0 D1 D2 D3 A B ~G Y ~W

MU X_4TO1

Our best 4-1 Multiplexer will be the one that is implemented using pass transistor layout

Pass transistor layout of 4 to 1 mux; DRC check passed

But there is a problem with this design, aNmos transistors cannot pass a good logic 1.

This could be corrected by using PMOS pass gate, but PMOS cannot pass a good logic 0. Therefore the optimal solution is to use both PMOS and NMOS transistors in a transmission gate arrangement. Requiring a total of 20 transistors which is still more efficient than a SSI design.

Complementary pass-transistor layout of 4-1 MUX

4-1 Mux final layout

Functionality test passed First design problem on weak logic 1 Solved A fast 4-1 multiplexer with only 8ps delays No initialization spike needed

Power consumption optimize Spike only occurs when clock on the selectors are change

Perfectly symmetric design Threshold attenuation eliminated because of the Pass transistor layout.

Full adder
U7
A B CIN SUM CARRY

FULL_ADDER

In our previous designs we have a Full adder using Mirrored CMOS circuits. This is a design of a full adder which can be implemented in such a way that the PMOS is arrange as mirrored version of the NMOS.

Transistor layout of the full adder using dsch3

Layout using microwind, DRC check passed output still need to be inverted

Functionality test passed. The circuit makes a spike to initialize after first power on. Because the circuit utilizes the mirrored CMOS time delay has been reduce to 17 picoseconds on low to high logic transition and 31 picoseconds on high to low.

Higher power consumption compared to the previous design. Significantly reducing the occurrence of having both PMOS and NMOS on Delays on transitions are decent Idd Max = 0.360 mA IddAvr = 0.009 mA

The circuit is not symmetric Vdd/2 = 0.457 V, 0.143V away to achieve perfect symmetry

ARITHMETIC LOGIC UNIT LAYOUT AND ANALYSIS

less A
D0 D1 D2 D3 A B ~G

U6
Y ~W

Result

MUX_4TO1

op opb

U5
D0 D1 Y ~W A B CIN

U7
SUM CARRY

set Cout

A ~G

MUX_2TO1

FULL_ADDER

binv

Cin

Logic gate Level Schematic

Transistor level schematic using dsch3

Metal Layout of ALU using Microwind in 90nm foundry; DRC check passed

Functionality Test
Operation a&b a or b a+b (addition) Op[1:0] MUX 4 00 01 10 Binv MUX 2 0 0 0

a-b (subtraction) a+~b+1

Less

10
11

1 ;Cin must also be 1

1 ;Cin must also be1

Operation a&b

Op[1:0] MUX 4 00

Binv MUX 2 0

Correct; Smooth output; spike at initialization

Correct; Smooth output; spike at initialization a or b 01 0

Correct; Smooth output; spike at initialization

a+b (addition)

10

Correct; Smooth output; spike at initialization 61 ps delay on high to low transition a-b (subtraction) a+~b+1 10 1 ;Cin must also be 1

Correct, spike cause by delays on input B, spike at initialization 61 ps delay on high to low transition Less 11 1 ;Cin must also be1

Correct; Smooth output; Resulting output will be clock less

VOLTAGE AND CURRENT ANALYSIS

Uniform power consumption, the condition that both Pmos and Nmos are on is eliminated. Those spikes inside the box is not included in the ALU functionality table OP[00] Binv 1 & OP[01] Binv 1

Conclusion

Our completed Arithmetic logic unit have a decent output with minimum disturbance on the output. Choosing the fastest components is a success, because less delay contributed to the final output. The use of transmission gates and pass transistors on our multiplexers not only make the circuit fast, it made the design easy to troubleshoot with less transistors used. A balance between speed and size is achieve but can be further optimize. On this work, we spend most of our time working on and perfecting the design and layout of the basic logic gates we tried so many designs including the use of universal logic gate NAND, but we still found that the worst case ratio will best meet our requirement.