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Structure of Instructions
Every instruction consists of an operational Code (OP-Code) and -if necessary- an address part for the operand(s).
OP-Code Address(es) Operand(s)
Z80: OP-Code 1 Byte (exceptions: in OPs using index registers the OP-Code is two bytes) the instruction set is not orthogonal
# of addresses: 0 1 2 3 R1 op R2 (A) op R (A1) op (A2) (A1) op (A2) R3 R R (A3)
Register Direct The Instruction has only an OP-Code, both source and destination registers are defined in this code
Ex: LD A,B (Load A with contents of B): A B, OP-Code 78H
Register Indirect The instruction has only the OP-Code, the destination register is defined in this code and a 16Bit register containing the address of the source operand Ex: LD A,(HL) (Load A from address contained in HL): A (HL), 7EH
Extended (Direct) The address of the operad is given as part of the instruction eg LD A,(1000H): A (1000H), OP-Code 3AH 00H 10H
OP-Code n m m n
memory
...
address operand
...
OP-Code offset
PC next OP-Code
...
PC PC+2 OP-Code (JR) x=e-2 next instruction
...
destination address: (PC + 2) + x = PC + e
...
operand
...
Bit
Direct addressing of a bit for bit manipulations eg SET 3,A (Set bit 3 of A to 1): A3 1, OP-Code CBH DFH (SET b,A: Ab 1, OP-Code CBH 11 b 111B)
...
# of Bytes 1 2
# of M Cycles 2 3
# of T states 7 11
Instruction Classes
Data Transfer Group Arithmetic Group Logical and Rotate Group Branch Group Stack, I/O, and Machine Contol Group Exchange, Block Transfer, and Search Group Bit Manipulation Group
OP Code Hex 78 21 00 07
Arithmetic Group
OP Code Hex 80 09
Description
BE
CP (HL)
Bitwise AND-operation of A A B A and B, result in A the contents of the memory location A - (HL) addressed by HL is subtracted from A, set flags, A unchanged
Description
control is tranferred to address 0100H control is transferred to address in PC + offset e if Carry-Flag is 0 control is transferred to subroutine at address 0100H, return address is stored on stack, SP is decremented by 2 control is transferred to address on top of stack (return address), SP is incremented by 2
CD 00 01
CALL 0100H
C9
RET
C1
POP BC
Description BC is copied to top of stack, SP is decremented by 2 top of stack is copied to BC, SP is incremented by 2
ED B8
LDDR
Description exchange of primary and alternative general purpose registers load location (DE) with location (HL), decrement DE, HL, and BC, repeat until BC = 0 compare location (HL) with accumulator, increment HL, decrement BC, set flags, A unchanged
ED A1
CPI
Symbolic Operation Z C4 * H6 1 *
H6 0 *