Microcontroller Architecture &

Interfacing Concepts

Facilitated By:
Shrikrishna.
C-DAC Bangalore

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Topics that will be covered in this Module
 Processor Architecture
 Internal Architecture of 8051 Microcontroller
 Cross Platform Development Model
 ALP & Addressing Modes
 Instruction Set Architecture
 Study of various on chip peripherals
 External interfacing Techniques

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  Timers & Counters

 Serial Communication
 Interrupt Handling

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Processor Architecture & Organization
Architecture
Architecture Refers to the Programmers view of the
computer or the users view of the computer.
 What will come in the Architectural Study
 Instruction set, visible registers, memory
management table structures and exceptional handling
model are all part of the architecture.
 Basically these are the things which are
programmable features of the processor.
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Processor Architecture & Organization
Organization (Implementation details)
Computer organization describes the user invisible
implementation of the architecture.
 What will come in the Organizational Study
 The pipeline structure, cache structure, table
walking hardware and translation look-aside buffer
are all the aspects of the organization.
 Basically these are the things which decide the
performance of a processor and are fixed they can’t
be changed by the programmer.
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 Basic Concepts
• Microprocessor Vs Microcontroller
• Microcontroller Classification
• Architecture Types
• CISC & RISC
• Memory Mapped IO & IO Mapped IO
• Embedded Development Environment

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 Micro Processors

• Micro Processor is the Integration of a

number of useful function in a single IC
Package .These functions are
1)Execute the stored set of instructions to
carry out user defined task.
2)Ability to access external memory chips for
both read and write data from and to the
memory
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 CPUs
• CPUs can be
– Microprocessors or Micro controllers

• Any CPU can be studied by knowing following

features of CPU
– Clock speed, Address bus size, Data bus size, Register size
– Register set, Instruction set, Address spaces
– Interrupt support
– Instruction and Data cache
– Memory management
– Protection features (user/supervisor modes)
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 Microprocessors:
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example ： Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

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 Microcontroller :

• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

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 Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. • for applications in which cost,
• expansive power and space are critical
• versatility • single-purpose
• general-purpose

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 Microprocessor Vs
Microcontroller
• Contains ALU,GP • In addition in built ROM,
Registers,SP,PC,Clock timing RAM, IO devices,Timers
circuit and interrupts ideal for applications in which
• Provides the advantage of cost & space are critical.
versatility to designer to
decide upon the additional
features required. • Many bit handling
• one or two bit handling instructions are present &
instructions & here the here the pins are
instruction set is aimed at programmable
expediting external memory • Requires less H/W, reduces
access process PCB size & increases
• Requires more H/W, increase reliabilit
in PCB size
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 Classification of Microcontrollers
• μc are classified into :
– 8 bit μc e.g.: Intel 8051, Motorola HC05
– 16 bit μc e.g.: Siemens 80167, Intel 80C196
– 32 bit μc e.g.: ARM, Power PC 8xxx
– 64 bit μc e.g.: Texas 64xxx series
– 128 bit μc e.g.:
• The number of bits indicate the internal data bus of a μc.
It shows how many bits of data the μc can process
simultaneously.

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 Embedded System
General Block Diagram

Sensor conditioning

Output interfaces
sensor
actuator
Microcontroller
sensor
(uC) indicator
sensor

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 MCS-51 “Family” of
Microcontrollers

• 8051 introduced by Intel in late 1970s

• Now produced by many companies in many
variations
• The most popular microcontroller – about
40% of market share
• 8-bit microcontroller
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(C ) The Contents of this document are the copyright of CDAC. No part of the contents may be used or reproduced without the prior permission of the author 16
 Memory Organization in 8051

• All 8051 devices have separate address spaces

for Program & Data Memory.
• Does this logical Separation of Data &
Program memory mean 8051 is Harvard
architected processor ???
• Data memory (RAM) occupies a separate
address space from program memory (ROM)

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Memory Access Ranges supported
by the 8051 Architecture
• The lowest 128 bytes of data memory are on chip.
• Up to 64k bytes of external RAM can be addressed in
the external Data Memory Space.
• Can we go beyond this size ?????
• Internal Program is 4k bytes in classic 8051 may vary
in 8051 variants.
• External Program Memory could also be present
limited by 64k bytes – Internal ROM size.

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 What goes into program memory ?
• Application Code
• System Startup code or Initialization code
• Interrupt Handlers
• Debug Monitor Code
• It is basically any piece of code which the processor
executes ( Fetches  Decode executes)
• What is the address range of program code ??
Ans. (0000h --- FFFFh) This range is decided by
what is the size PC.

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 Memory mapping in 8051
ROM memory map in 8051 family

4k 8k 32k
0000H 0000H 0000H

0FFFH
DS5000-32

1FFFH
8751
AT89C51
8752
AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

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 Who Programs the code memory ?
• Is it the Application code written by the
programmer.
• Is it the system which does the burning of
your code into the ROM.
• Answer is it can be done in both ways.
• We have two ways of programming the
Flash Memory
• ISP and IAP.
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 The 2 ways of programming the Flash

In-Application Programming (IAP)

In-System Programming (ISP)

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 In-System Programming
• The Flash device can be reprogrammed via UART/Parallel interface
without being removed from the target.
• ISP is accomplished by having a downloader firmware
preprogrammed into the on board memory which provides the
interface for the ISP.
• In this case the processor is put in a special boot or programming
mode.
• The application needs to stopped during the reprogramming process.
Serial
Port

ISP Software

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 In-Application Programming
User can program the Flash from an application running in RAM
• This is done by the by calling the functions in the boot loader area by the application code to do the required operation on the flash memory.
• The Flash could be also programmed using the serial or Ethernet interface (but not directly)
• First the image is copied into the RAM by running the appropriate command of the bootloader .
• Then use the IAP command “Copy RAM to Flash” to program the Flash from RAM.
•

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 What goes into the Data Memory
• Naturally the Data goes into Data Memory.
• How does it go ????
• This is by the Instructions……
• You can read and write by instructions into this memory
• Can you in the similar way read the program memory.
( Through instructions )
• But why do you want to read program memory ??
• Is it to read Instructions or Data.

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 DATA Memory Organization in
8051

• 128 bytes of internal memory is grouped as:

• Register Bank ( 00 h --- 1f h) 32 bytes
• Bit Addressable Area ( 20 h --- 2f h) 16 bytes
• Scratch Pad Area ( 30 h --- 7f h) 80 bytes

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 Lower 128 bytes of internal RAM

Scratch Pad Area

(30-7F)
SP=07
Bit & Byte Addressable RS1=0
Area (20-2F) RS0=0
Bank3(18-1F)
Bank2 (10-17)
Bank1(08-0F)
Bank0 (00-07)

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 REGISTER BANK

REGISTER BANK 0 REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3

R7 07h R7 0Fh R7 17h R7 1Fh

R0 00h R0 08h R0 10h R0 18h

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 On-Chip DATA Memory:
RAM
Internal RAM

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 Registers
1F
Four Register Banks
Bank 3 Each bank has R0-R7
18
17

Bank 2
10
0F

Bank 1
08
07 R7
06 R6
05 R5
04 R4
03 R3 Bank 0
02 R2
01 R1
00 R0

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 Bit Addressable Memory
2F 7F 78
20h – 2Fh (16 locations X
2E 8-bits = 128 bits)
2D
2C
Bit addressing:
2B
mov C, 1Ah
2A
29
or
28 mov C, 23h.2
27
26
25
24
1A
23
22 10

21 0F 08
20 07 06 05 04 03 02 01 00

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 • To select the register banks, there are 2 bits
present in PSW:
• RS0
• RS1

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 BIT ADDRESSABLE AREA

• 16 eight bit locations, ranging from 20h to 2Fh

are bit addressable.
16 locations * 8 bits = 128 bits

i.e.., 128 bits can be individually addressed.

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 • These bits can be addressed as
20.0h to 2F.7h
or
00h to 7Fh.

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 SCRATCH PAD AREA

• Locations from 30h to 7Fh are available as

Scratch Pad area.

• Can store data such as partial results and such

variables.
i.e., as general purpose locations

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 Thus,
4 - register banks => 32 bytes
1 bit addressable area => 16 bytes
1 scratch pad area => 80 bytes
128 bytes of
INTERNAL RAM

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 Special Function Registers
DATA registers

CONTROL registers

•Timers
•Serial ports Addresses 80h – FFh
•Interrupt system
•Analog to Digital converter Direct Addressing used to
•Digital to Analog converter access SPRs
•Etc.

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 (Address - 0E0h)

• 8 - Bit Register
• Used for operations such as
• Addition
• Subtraction
• Multiplication
• Division &
• Bit Manipulations
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• Used for Data Transfer Between 8051 & External
memory
• Used to store Results obtained from Arithmetic as
well as logical Operations
• Bit Addressable Register

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 (Address - 0F0h)

• Used for direct Multiplication & Division

operations with Accumulator.
• Can be used as general purpose storage location
with its direct address 0F0h.
• Bit Addressable Register.

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 (Address - 0D0h)
• 8 - Bit Register
• Consists of 5 FLAGS
• 4 MATH FLAGS
• Carry
•Auxiliary Carry
• Parity
• Overflow
• 1 USER DEFINED FLAG
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 Bit Flag Description

7 CY Carry flag; used in arithmetic, jump,

6 AC
5 F0
4 RS1
3 RS0
rotate and Boolean instructions.
Auxiliary carry; used for BCD
arithmetic
User defined flag 0
Register bank select bit-1
Register bank select bit-0

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 RS1 RS0 Bank Select
0 0 Bank - 0
0 1 Bank - 1
1 0 Bank - 2
1 1 Bank - 3

Bit Flag Description

2 OV Overflow flag; used in arithmetic

instructions
1 - Reserved for future use

0 P Parity flag; shows parity of register A;

‘1’ => Odd parity; ‘0’ => Even Parity

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 (Address - 81h)

• 8 - Bit Register.
• Stack Pointer is Initialized to 07h at RESET
condition.
• Instructions such as PUSH and POP modify SP.
• UP - GROWING stack.
• Can be reinitialized to any desired location by the
user.
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 (Direct Address - NIL)

• 16 - Bit Register
• Used to hold the Address of external Data
Memory.
• Can be used as two individual 8 - bit registers
such as
• Data Pointer High (DPL) - Address 82h
• Data Pointer Low (DPH) - Address 83h
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 DPH 83h DPL 82h

DPTR

• No direct address is assigned for DPTR but can be

individually addressed

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 (Direct Address - NIL)

• 16 - Bit Register
• Used to hold the Address of the next instruction
to be executed
• Not directly accessible to the programmer.
• No internal address.

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 • Group of registers used for specific purposes
in 8051 microcontroller mainly to
• Configure
• Control, &
• operate.
• Uses address locations from 80h to 0ffh.
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 • Accumulator - A*
• Register B - B*
• Program Counter - PC
• Data Pointer - DPTR
• Stack Pointer - SP
• Program Status Word - PSW
• Ports - P0* , P1* , P2* , P3* .
• Timer Load Registers - TL0/1 & TH0/1
• Timer Config. & Ctrl Reg. - TCON*, TMOD
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 • Serial Comm. Control Register - SCON*
• Serial Comm. Buffer Register - SBUF
• Program Control Register - PCON
• Interrupt Enable Register - IE*
• Interrupt Priority Register - IP*

NOTE:
Registers marked with * are both Bit as well as Byte Addressable

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 • External bus of 8051 is grouped
into 4 ports namely:
• Port - 0
• Port - 1
• Port - 2
• Port - 3

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 • These ports supports all the three types of
buses namely:

• Address Bus,
• Data Bus, &
• Control Bus.

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• All the ports are Bi - directional.
• All the ports are Bit as well as Byte addressable.
• The addresses of the ports are as shown below:

PORTS ADDRESS
PORT 0 080h
PORT 1 090h
PORT 2 0A0h
PORT 3 0B0h

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 Internal Data Memory in 8052

Accessible by Accessible by direct

indirect addressing Addressing(SFR Area)
(80-FF)=128 bytes (80-FF)=128 bytes

Accessible by direct
& indirect addressing
(00-7F)=128 bytes

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 INTERNAL READ ONLY MEMORY (ROM)

0FFFh

4 Kbytes of
Internal
ROM

0000h
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 EXTERNAL MEMORY ORGANIZATION

• 8051 Microcontroller supports up-to

• 64 Kbytes of Data Memory
• 64 Kbytes of Program Memory

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• 8051 Microcontroller is interfaced and accessed
to external memory using 16 address lines
available on PORT0 and PORT 2.
• Address and Data lines are multiplexed using
PORT0.
• De - multiplexing of the address and data lines
are done by ALE signal

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 DATA MEMORY ORGANIZATION

• 8051 Microcontroller supports

• 64 Kbytes of External Data Memory
• 128bytes of Internal Data Memory

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 External Memory Interface
ADD-H

8051 Memory
Latch ADD-L

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 • External Data Memory is accessed using
16 - bit address lines.
RD bar and WR bar are used as strobe signals
• Address range : 0000h to 0FFFFh
- External Memory
00h to 7Fh
- Internal Memory
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 FFFFh
FFh
SFR’s
Direct
Addressing
64 Kbytes
only
80h of
External
7Fh Direct Memory
& In Direct
Addressing
only
00h
0000h

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 PROGRAM MEMORY ORGANIZATION

• 8051 Microcontroller supports

• 64 Kbytes of External Program Memory
• 4Kbytes of Internal Program Memory plus
60K bytes of External Program Memory.

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• External Program Memory is accessed using
16 - bit address lines.
 PSEN is used as read strobe for external
program memory
• Address range : 0000h to 0FFFFh

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 FFFFh
FFFFh
60Kbytes
of External
ROM
1000h

+ 64 Kbytes
OR of
External
0FFFh ROM

4Kbytes of
Internal 0000h
ROM
0000h
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 8051 Memory Structure

External
External
(64Kb)
indirect direct
(128) (128)

EA bar=0 EA bar=1 direct

External Internal & indirect
(128)

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