Buffer and FF Insertion

Slides from Charles J. Alpert

IBM Corp.

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Talk Outline
Introduction

Buffer insertion
Van Ginneken dynamic programming
Extensions

Interconnect planning
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Simple Buffer Insertion Problem
Given: Source and sink locations, sink capacitances
and RATs, a buffer type, source delay rules, unit
wire resistance and capacitance
Buffer
RAT
1
RAT
2
RAT
3
RAT
4
s
0
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Simple Buffer Insertion Problem
Find: Buffer locations and a routing tree such that
slack at the source is minimized
RAT
2
RAT
3
RAT
4
RAT
1
s
0
)} , ( ) ( { min ) (
0 4 1 0 i i i
s s delay s RAT s q

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Slack Example
RAT = 400
delay = 600
RAT = 500
delay = 350
RAT = 400
delay = 300
RAT = 500
delay = 400
slack = -200
slack = +100
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Elmore Delay
2 2 2 1 1
) ( ) ( C R C C R C A Delay
A B
C
R
1
R
2
C
1
C
2
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Common Approaches
Iteratively insert buffers
Closed-form solutions (2 pin nets)
Dynamic programming
Simultaneous constructions
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Van Ginnekens Classic Algorithm
Optimal for multi-sink nets
Quadratic runtime
Bottom-up from sinks to source
Generate list of candidates at each node
At source, pick the best candidate in list
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Key Assumptions
Given routing tree
Given potential insertion points
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Generating Candidates
(1)
(2)
(3)
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Pruning Candidates
(3)
(a)
(b)
Both (a) and (b) look the same to the source.
Throw out the one with the worst slack
(4)
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Candidate Example Continued
(4)
(5)
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Candidate Example Continued
After pruning
(5)
At driver, compute which candidate maximizes
slack. Result is optimal.
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Merging Branches
Right
Candidates
Left
Candidates
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Pruning Merged Branches
Critical
With pruning
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Van Ginneken Example
(20,400)
(20,400)
(30,250)
(5, 220)
Wire
C=10,d=150
Buffer
C=5, d=30
(20,400)
Buffer
C=5, d=50
C=5, d=30
Wire
C=15,d=200
C=15,d=120
(30,250)
(5, 220)
(45, 50)
(5, 0)
(20,100)
(5, 70)
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Van Ginneken Example Contd
(20,400)
(30,250)
(5, 220)
(45, 50)
(5, 0)
(20,100)
(5, 70)
(5,0) is inferior to (5,70). (45,50) is inferior to (20,100)
(20,400)
(30,250)
(5, 220)
(20,100)
(5, 70)
(30,10)
(15, -10)
Pick solution with largest slack, follow arrows to get solution
Wire C=10
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Van Ginneken Recap
Generate candidates from sinks to source
Quadratic runtime
Adding a buffer adds only one new candidate
Merging branches additive, not multiplicative
Optimal for Elmore delay model
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Optimal Extensions
Multiple buffer types
Inverters
Polarity constraints
Controlling buffer resources
Capacitance constraints
Blockage recognition
Wire sizing
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Multiple Buffer Types
(1)
(2)
Time complexity increases from O(n
2
) to O(n
2
B
2
)
where B is the number of different buffer types
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Inverters
(1)
(2)
Maintain a + and a - list of candidates
Only merge branches with same polarity
Throw out negative candidates at source
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Polarity Constraints
Some sinks are positive, some negative
Put negative sinks into - list
- list
- list
+ list
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Controlling Buffering Resources
3
2
1
0
(C
1
, q
1
, 3), (C
2
, q
2
, 3), (C
3
, q
3
, 3)
(C
4
, q
4
, 2), (C
5
, q
5
, 2)
(C
6
, q
6
, 1), (C
7
, q
7
, 1), (C
8
, q
8
, 1)
(C
9
, q
9
, 0)
(C
1
, q
1
), (C
2
, q
2
), (C
3
, q
3
) (C
4
, q
4
), (C
5
, q
5
)
(C
6
, q
6
), (C
7
, q
7
), (C
8
, q
8
) (C
9
, q
9
)
Before, maintain list of capacitance slack pairs
Now, store an array of lists, indexed by # of buffers
Prune candidates with inferior cap, slack, and #buffers
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Buffering Resource Trade-off
-4000
-3000
-2000
-1000
0
1000
0 1 2 3 4 5 6 7
# of Buffers
S
l
a
c
k

(
p
s
)

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Capacitance Constraints
Each gate g drives at most C(g) capacitance
When inserting buffer g, check downstream
capacitance.
If bigger than C(g), throw out candidate
Total cap = 500 ff
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Blockage Recognition
Delete insertion
points that run
over blockages

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Other Extensions
Simultaneous driver sizing
Modeling effective capacitance
Higher-order interconnect delay
Slew constraints
Noise constraints
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Driver Sizing
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Driver Sizing
Driver behaves like buffer
Pick driver with the best slack
Implications upstream in timing graph
Delay penalty for large input capacitance
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
p-Models
Van Ginneken candidate: (Cap, slack)
C
C
n

R
C
f

Replace Cap with p-model (C
n
, R, C
f
)
Total capacitance preserved: C
n
+ C
f
= C
R represents degree of resistive shielding
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Computing Gate Delay
When inserting buffer, compute effective
capacitance from p-model

C
ef
f

Use effective instead of lumped
capacitance in gate delay equation
Optimality no longer guaranteed

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Higher-order Interconnect Delay
Moment matching with first 3 moments
Previously: candidate (p-model, slack)
Now: candidate (p-model, m
1
, m
2
, m
3
)
Given moments, compute slack on the fly
Bottom-up, efficient moment computation
Problem: guess slew rate
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Slew Constraints
When inserting buffer, compute slews
to gates driven by buffer
If slew exceeds target, prune candidate
Difficulty: unknown gate input slew
Slew 300 ps
Slew 350 ps
?
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Noise Constraints
Each gate has acceptable noise threshold
Compute cumulative noise for each wire
via Devgan noise metric
Throw out candidates that violate noise
Not in production code

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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Extensions Recap
Multiple buffer types, including inverters
Polarity constraints
Controlling buffer resources
Slew, capacitance, and noise constraints
Blockage recognition
Driver sizing
Higher-order delay modeling
Wire sizing
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Talk Outline
Introduction
Buffer insertion
Van Ginneken dynamic programming
Extensions

Interconnect planning
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
What is the Problem?
DSM timing closure
Squeeze buffers into tight spaces
Alleviate hot spots, local wire congestion
Getting worse
Handle wire congestion, buffering
resources early
Acknowledge these constraints when
floorplanning
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Which Floorplan Is Better?
Timing analysis worthless
Interconnect synthesis, electrical
correction, routing, extraction
Days to find answer
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Buffer Explosion
Past Present
Number of buffers triples each generation
800K buffers in 0.05 micron technology
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Buffer Block Planning
Create blocks between macros just for
holding buffers
Adjust floorplan accordingly
Computing size/#/location of blocks
Analyze 2-pin nets
Find feasible regions
Assign buffers with smallest region
Combine buffers into blocks
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Feasible Regions
feasible region
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Optimization Strategies for Physical Synthesis and Timing Closure ICCAD-2001
Buffer Block Planning Trade-offs
Goods
Buffer locations flexibile
Global view, buffers most difficult ones first
Bads
Wire congestion around blocks
Dont have timing information
Some nets still cannot be buffered/routed