1

EE462L, Spring 2014

Implementation of Unipolar PWM
Modulation for H-Bridge Inverter

(pre-fall 2009 - but discrete components
provide a better sense of how this circuit
operates)
2
AB B A load
V V V V

Switching rules


H-Bridge Inverter Basics Creating AC from DC

Vdc
Load
A+ B+
A B
Va

Vb

Either A+ or A is closed,
but never at th e same time
Either B+ or B is closed,
but never at the same time
Can use identical isolated firing signals
for A+, A, with inverting and non-
inverting drivers to turn on, turn off
simultaneously
The A+, A firing signal is a scaled
version of Va
The B+, B firing signal is a scaled
version of Vb
The difference in the two firing signals
is a scaled version of Vab
Same idea for B+, B
!
3



Vcont > Vtri , close switch A+, open
switch A , so voltage Va = Vdc

Vcont < Vtri , open switch A+, close
switch A , so voltage Va = 0

Vcont > Vtri , close switch B+, open
switch B , so voltage Vb = Vdc

Vcont < Vtri , open switch B+, close
switch B , so voltage Vb = 0
Vcont Vtri Vcont
Implementation of Unipolar PWM
Vcont is usually a sinewave, but it can also be a music signal.
V
tri
is a triangle wave whose frequency is at least 30 times greater
than Vcont.
The implementation rules are:
Vcont is the input signal we want to amplify at the output of the inverter.
Ratio m
a
= peak of control signal divided by peak of triangle wave
Ratio m
f
= frequency of triangle wave divided by frequency of control signal
!
4
Vdc
Vdc
V
load
Progressively
wider pulses
at the center
(peak of
sinusoid)
Progressively
narrower pulses
at the edges
Unipolar Pulse-Width
Modulation (PWM)
Implementation of Unipolar PWM Modulation
for H-Bridge Inverter
!
5
The four firing circuits do not have the same ground
reference. Thus, the firing circuits require isolation.

Vdc
(source of power delivered to load)
Load
A
+
B
+

A



B



Local ground
reference for A
+

firing circuit
Local ground
reference for B
+

firing circuit
Local ground
reference for B


firing circuit
Local ground
reference for A


firing circuit
S
S
S
S
!
6
7
This years circuit
8



8 5
Comp

1 4

270k





V
tri
V
cont
V
cont
270k
1k
1.5k
1.5k
V(A+,A)
12V
from DC-DC chip

+12V
from DC-DC chip

Common (0V) from DC-DC chip

+12V
12V
Comparator Gives V(A+,A)
wrt. Common (0V)
V
cont
> V
tri
V
cont
< V
tri
+24V
0V
V
cont
> V
tri
V
cont
< V
tri
Use V(A+,A) wrt. 12V
Output of the Comparator Chip
Since the comparator
compares signals that can be
either positive or negative, the
comparator must be powered
by V supply
9



8 5
Comp

1 4

270k





V
tri
V
cont
V
cont
270k
1k
1.5k
1.5k
V(B+,B)
12V
from DC-DC chip

+12V
from DC-DC chip

Common (0V) from DC-DC chip

+12V
12V
Comparator Gives V(B+,B)
wrt. Common (0V)
V
cont
> V
tri
V
cont
< V
tri
+24V
0V
V
cont
> V
tri
V
cont
< V
tri
Use V(B+,B) wrt. 12V
Output of the Comparator Chip
Since the comparator
compares signals that
can be either positive or
negative, the
comparator must be
powered by V supply
10
This years circuit
11




Wall wart Op amps
Notes for the above converter chip keep the input and output sections isolated from each
other.

When energizing your circuit, check the +12V and 12V outputs to make sure they are OK. Low
voltages indicate a short circuit in your wiring, which can burn out the chip in a few minutes.
Input Output
12



Triangle wave generator
13


Dual Op Amp

Dual Comparator
14

Figure 9. Output of triangle-wave generator (with respect to
protoboard common)

Indicates DC
offset

Figure 10. Rise and fall times of the triangle wave
Equal rise and fall times
15


Figure 11. Output of high-pass filter
DC offset
minimized
Save screen
snapshot #1
0V
+4V
4V
16

Figure 12. Output control voltages V(A
+
,A

) and V(B
+
,B

), with respect to
protoboard 12V reference, with V
cont
= 0 (i.e., the m
a
= 0 case)

Save screen
snapshot #2
For m
a
= 0, use a
multimeter to check the
following DC voltages
with respect to 12V ref:

V(A
+
,A

) 11.8Vdc
V(B
+
,B

) 11.8Vdc
0V
+24V
0V
+24V
17


Figure 14. Output control voltage V(A
+
,A

) on top, and V(B

+
,B

) on bottom, with respect

to protoboard 12V reference, with m
a
> 0 (the situation shown is where V
cont
is negative)


Figure 13. Output control voltage V(A
+
,A

) on top, and V(B

+
,B

) on bottom, with respect

to protoboard 12V reference, with m
a
> 0 (the situation shown is where V
cont
is positive)
Save screen
snapshot #3
0V
+24V
0V
+24V
0V
+24V
0V
+24V
18

Figure 15. Idealized V
load
, with m
a
just into the overmodulation region

split
split
Save screen
snapshot #4
0V
+24V
24V
19


Figure 17. Idealized V
load
observed in the scope averaging mode, with m
a
just into
the overmodulation region


Figure 16. Idealized V
load
observed in the scope averaging mode, with m
a
in the
linear region
Save screen
snapshot #5
0V
+24V
24V
0V
+24V
24V
Flat toping indicates
the onset of
overmodulation
20


Figure 18. Idealized V
load
observed in the scope averaging mode, with m
a
almost into
the saturation (i.e., square wave) region

0V
+24V
24V
Approaching a
square wave
21


Figure 19. FFT of idealized V
load
in the linear region with m
a
1.0, where the
frequency span and center frequency are set to 100kHz and 50kHz, respectively
2f
tri
cluster (46kHz)
4f
tri
cluster
(92kHz)
60Hz
component