Oxidation

2001 by Prentice Hall Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda

Oxidation
Oxidation is the process which converts
silicon on the wafer into silicon dioxide.
Oxide Growth
Oxide Growth is a natural phenomenon that
occurs by exposing the silicon wafer to
oxygen at an elevated temperature
We use the term grow to indicate that
temperature is used to cause the oxide to
grow out of the silicon semiconductor
material.
Diffusion Area of Wafer Fabrication
Test/Sort
Thin Films
Implant
Diffusion Etch
Polish
Photo
Completed wafer
Wafer fabrication (front-end)
Unpatterned
wafer
Wafer start
Used with permission from Advanced Micro Devices
Figure 10.1

Oxide Film
Nature of Oxide Film
Uses of Oxide Film
Device Protection and Isolation
Surface Passivation
Gate Oxide Dielectric
Dopant Barrier
Dielectric Between Metal Layers

Nature of Oxide Film
Silicon dioxide is an insulator
Atomic structure of silicon diode is
tetrahedron cell
Silicon dioxide is a form of intrinsic (pure)
glass with a melting temperature of 1732
o
C

Atomic Structure of Silicon Dioxide
Silicon
Oxygen
Used with permission from International SEMATECH
Figure 10.2

Uses of Oxide Film
Device Protection and Isolation

Silicon dioxide protect sensitive device in the
silicon.
The hard silicon dioxide layer will protect the
silicon from scratches and processing damage
that might occur during fabrication

Uses of Oxide Film
Surface Passivation

Control the leakage current of junction
devices.

Field Oxide Layer
p+ Silicon substrate
p- Epitaxial layer
n-well p-well
Field oxide isolates active regions from each other.
Figure 10.3

Uses of Oxide Film

A thin layer of oxide is used as the
dielectric material for the important gate
oxide structure common in MOS
technology.
Silicon dioxide has a high dielectric
strength of 10
7
volts/cm and high resistivity
of 10
17
ohms-cm

Gate Oxide
p- Epitaxial layer
n-well p-well
Polysilicon gate
Figure 10.4

Oxide Layer Dopant Barrier
Phosphorus implant
p- Epitaxial layer
n-well
Barrier oxide
Figure 10.5

Oxide Application
Table 10.1
Oxide Applications: Native Oxide
Purpose: This oxide is a contaminant and generally
undesirable. Sometimes used in memory storage or
film passivation.
Comments: Growth rate at room temperature is 15 per hour up
to about 40 .
p
+
Silicon substrate
Silicon dioxide (oxide)
Table 10.1A

Table 10.1
Oxide Applications: Field Oxide
Purpose: Serves as an isolation barrier between individual
transistors to isolate them from each other.
Comments: Common field oxide thickness range from 2,500
to 15,000 . Wet oxidation is the preferred method.
Field oxide
Transistor site
p
+
Silicon substrate
Table 10.1B

Table 10.1
Oxide Applications: Gate Oxide
Purpose: Serves as a dielectric between the gate and source-
drain parts of MOS transistor.
Comments: Growth rate at room temperature is 15 per hour
up to about 40 . Common gate oxide film
thickness range from about 30 to 500 . Dry
oxidation is the preferred method.
Gate oxide
Transistor site
p
+
Silicon substrate
Source Drain
Gate
Table 10.1C

Table 10.1
Oxide Applications: Barrier Oxide
Purpose: Protect active devices and silicon from follow-on
processing.
Comments: Thermally grown to several hundred Angstroms
thickness.
Barrier oxide
Diffused resistors
Metal
p
+
Silicon substrate
Table 10.1D

Table 10.1
Oxide Applications: Dopant Barrier
Purpose: Masking material when implanting dopant into
wafer. Example: Spacer oxide used during the
implant of dopant into the source and drain regions.
Comments: Dopants diffuse into unmasked areas of silicon by
selective diffusion.
Dopant barrier
spacer oxide
Ion implantation
Gate
Spacer oxide protects narrow
channel from high-energy implant
Table 10.1E

Table 10.1
Oxide Applications: Pad Oxide

Purpose: Provides stress reduction for Si
3
N
4

Comments: Thermally grown and very thin.
Passivation Layer
ILD-4
ILD-5
M-3
M-4
Pad oxide
Bonding pad metal
Nitride
Table 10.1F

Table 10.1
Oxide Applications: Implant Screen Oxide
Purpose: Sometimes referred to as sacrificial oxide, screen
oxide, is used to reduce implant channeling and
damage. Assists creation of shallow junctions.
Comments: Thermally grown
Ion implantation
Screen
oxide
High damage to upper Si
surface + more channeling
Low damage to upper Si
surface + less channeling
p
+
Silicon substrate
Table 10.1G

Passivation layer
ILD-4
ILD-5
M-3
M-4
Interlayer oxide
Bonding pad metal
Table 10.1
Oxide Applications: Insulating Barrier between
Metal Layers

Purpose: Serves as protective layer between metal lines.
Comments: This oxide is not thermally grown, but is deposited.
Table 10.1H

Thermal Oxidation
Thermal Oxidation is most commonly
technique to grow Silicon dioxide on
Silicon, and is usually carried out a
temperature range of 750
o
C to 1100
o
C

Thermal Oxidation Growth
Chemical Reaction for Oxidation
Dry oxidation
Wet oxidation
Oxidation Growth Model
Oxide silicon interface
Use of chlorinated agents in oxidation
Rate of oxide growth
Factors affecting oxide growth
Initial growth phase
Selective oxidation
LOCOS
STI

Dry Oxidation
Thermal Oxide is grown by a chemical
reaction between silicon and oxygen
Chemical Reaction
Si (solid) + O
2
(gas) SiO
2
(solid)

Wet Oxidation
Its occurs when water vapor is introduced in
the reaction
Chemical Reaction

Si (solid) + 2H
2
O (vapor)
SiO
2
(solid) + 2H
2
(gas)

Oxide Thickness Ranges for Various
Requirements
Semiconductor Application Typical Oxide Thickness,
Gate oxide (0.18 m generation) 20 60
Capacitor dielectrics 5 100
Dopant masking oxide
400 1,200
(Varies depending on dopant, implant
energy, time & temperature)
STI Barrier Oxide 150
LOCOS Pad Oxide 200 500
Field oxide 2,500 15,000
Table 10.2

Dry Oxidation Time (Minutes)
O
x
i
d
e

t
h
i
c
k
n
e
s
s

(
m
)

(100) Silicon
Time (minutes)
10 10
4
10
2
10
3

0.01
0.1
1.0
10.0
Figure 10.6

Wet Oxygen Oxidation
HCl N
2
O
2
H
2

Gas panel
Furnace
Burn box
Scrubber
Exhaust
Figure 10.7

Consumption of Silicon during Oxidation
t
0.55t
0.45t
Before oxidation After oxidation
Figure 10.8

Liquid-State Diffusion
Figure 10.9

Charge Buildup at Si/SiO2 Interface
Oxygen Silicon
Positive charge
Silicon
SiO
2

Figure 10.10

Diffusion of Oxygen Through Oxide Layer
Figure 10.11

Si
SiO
2

O, O
2

Oxide-silicon
interface
Oxygen-oxide
interface
Oxygen supplied to
reaction surface
Linear & Parabolic Stages for Dry
Oxidation Growth at 1100C
Figure 10.12

}
100 200 300 400 500
Oxidation time (minutes)
4,000
2,000
3,000
1,000
O
x
i
d
a
t
i
o
n

t
h
i
c
k
n
e
s
s

Approximate linear region
LOCOS Process
3. Local oxidation of silicon
Cross section of LOCOS field oxide
(Actual growth of oxide is omnidirectional)
1. Nitride deposition
Pad oxide
(initial oxide)
2. Nitride mask & etch
Silicon
Nitride
SiO
2
growth
4. Nitride strip
SiO
2

SiO
2

Nitride
Silicon
Figure 10.13

Selective Oxidation and Birds Beak Effect
Silicon oxynitride
Nitride oxidation mask
Birds beak region
Selective oxidation
Pad oxide
Silicon substrate
Silicon dioxide
Figure 10.14

STI Oxide Liner
Cross section of shallow
trench isolation (STI)
Silicon
Trench filled with
deposited oxide
Sidewall liner
1. Nitride deposition
Pad oxide
(initial oxide)
2. Trench mask and etch
Silicon
Nitride
4. Oxide planarization (CMP)
5. Nitride strip
Oxide
3. Sidewall oxidation and trench fill
Oxide over
nitride
Figure 10.15

Furnace Equipment
Horizontal Furnace
Vertical Furnace
Rapid Thermal Processor (RTP)

Horizontal and Vertical Furnaces
Table 10.3

Performance
Factor
Performance
Objective
Horizontal Furnace Vertical Furnace
Typical wafer
loading size
Small, for process
flexibility
200 wafers/batch 100 wafers/batch
Clean room
footprint
Small, to use less
space
Larger, but has 4 process
tubes
Smaller (single process
tube)
Parallel processing
Ideal for process
flexibility
Not capable Capable of
loading/unloading wafers
during process, which
increases throughput
Gas flow
dynamics (GFD)
Optimize for
uniformity
Worse due to paddle and
boat hardware. Bouyancy
and gravity effects cause
non-uniform radial gas
distribution.
Superior GFD and
symmetric/uniform gas
distribution
Boat rotation for
improved film
uniformity
Ideal condition Impossible to design Easy to include
Temperature
gradient across
wafer
Ideally small Large, due to radiant
shadow of paddle
Small
Particle control
during
loading/unloading
Minimum particles Relatively poor Improved particle control
from top-down loading
scheme
Quartz change
Easily done in short
time
More involved and slow Easier and quicker, leading
to reduced downtime
Wafer loading
technique
Ideally automated Difficult to automate in a
successful fashion
Easily automated with
robotics
Pre-and post-
process control of
furnace ambient
Control is desirable Relatively difficult to
control
Excellent control, with
options of either vacuum or
neutral ambient
Horizontal Diffusion Furnace
Photograph courtesy of International SEMATECH
Photo 10.1

Vertical Diffusion Furnace
Photograph courtesy of International SEMATECH
Photo 10.2

Block Diagram of Vertical Furnace System
Heater 1
Heater 2
Heater 3
Pressure
controller
Gas flow
controller
Wafer handler
controller
Boat
loader
Exhaust
controller
Temperature
controller
Microcontroller
Wafer load/unload system
Boat motor drive system
Quartz boat
Quartz process chamber
Three-zone
heater
Gas
panel
Process gas
cylinder
Exhaust
Figure 10.16

Vertical Furnace Process Tube
Heating jacket
Quartz tube
Three-zone
heating
elements
End cap
Figure 10.17

Heater Element Power Distribution
Heater element
transformer
204 - 480 VAC 3f
SCRs SCRs
SCRs
Trigger
circuit
Zone 1 Zone 2 Zone 3
Furnace heater elements
Figure 10.18

Locations of Thermocouples in the
Furnace Chamber
Heater 1
Heater 2
Heater 3
Thermocouple measurements
Temperature
controller
Profile TCs
C
o
n
t
r
o
l

T
C
s

O
v
e
r
t
e
m
p
e
r
a
t
u
r
e

T
C
s

System
controller
TC
Figure 10.19

Common Gases used in Furnace Processes
Gases Classifications Examples
Inert gas Argon (Ar), Nitrogen (N
2
)
Reducing gas Hydrogen (H
2
) Bulk
Oxidizing gas Oxygen (O
2
)
Silicon-precursor gas Silane (SiH
4
), dichlorosilane (DCS) or (H
2
SiCl
2
)
Dopant gas Arsine (AsH
3
), phosphine (PH
3
) Diborane (B
2
H
6
)
Reactant gas Ammonia (NH
3
), hydrogen chloride (HCl)
Atmospheric/purge gas Nitrogen (N
2
), helium (He)
Specialty
Other specialty gases Tungsten hexafluoride (WF
6
)
Table 10.4

Burn Box to Combust Exhaust
O
2

O
2

Combustion chamber
(burn box or flow
reactor)
Filter
Residue
Excess combustible gas burns in
hot oxygen rich chamber
Gas from furnace
process chamber
To facilitys
exhaust system
Wet
scrubber
Recirculated
water
Figure 10.20

Thermal Profile of Conventional Versus
Fast Ramp Vertical Furnace
Reprinted from the June 1996 edition of Solid State Technology,
copyright 1996 by PennWell Publishing Company.
Figure 10.21

0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
1200

1000

800

600

400
1200

1000

800

600

400
Time (minutes) Time (minutes)
T
e
m
p
e
r
a
t
u
r
e

(
C
)

T
e
m
p
e
r
a
t
u
r
e

(
C
)

Fast Ramp Conventional
The Main Advantages
of a Rapid Thermal Processor
Reduced thermal budget
Minimized dopant movement in the silicon
Ease of clustering multiple tools
Reduced contamination due to cold wall heating
Cleaner ambient because of the smaller chamber
volume
Shorter time to process a wafer (referred to as
cycle time)

Comparison of Conventional Vertical
Furnace and RTP
Vertical Furnace RTP
Batch Single-wafer
Hot wall Cold wall
Long time to heat and cool batch Short time to heat and cool wafer
Small thermal gradient across wafer Large thermal gradient across wafer
Long cycle time Short cycle time
Ambient temperature measurement Wafer temperature measurement
Issues: Issues:
Large thermal budget Temperature uniformity
Particles Minimize dopant movement
Ambient control Repeatability from wafer to wafer
Throughput
Wafer stress due to rapid heating
Absolute temperature measurement
Table 10.5

Rapid Thermal Processor
Temperature
controller
Axisymmetric lamp array
Wafer
Reflector plate
Optical fibers
Pyrometer
Heater head
Feedback voltages
Setpoint voltages
Figure 10.22

Rapid Thermal Processor
Photograph courtesy of Advanced Micro Devices, Applied Materials 5300 Centura RTP
Photo 10.3

RTP Applications
Anneal of implants to remove defects and activate
and diffuse dopants
Densification of deposited films, such as
deposited oxide layers
Borophosphosilicate glass (BPSG) reflow
Anneal of barrier layers, such as titanium nitride
(TiN)
Silicide formation, such as titanium silicide
(TiSi
2
)
Contact alloying

Oxidation Process
Pre Oxidation Cleaning
Oxidation process recipe
Quality Measurements
Oxidation Troubleshooting

Critical Issues for Minimizing Contamination
Maintenance of the furnace and associated
equipment (especially quartz components)
for cleanliness
Purity of processing chemicals
Purity of oxidizing ambient (the source of
oxygen in the furnace)
Wafer cleaning and handling practices

Thermal Oxidation Process Flow Chart
Wet Clean
Chemicals
% solution
Temperature
Time
Oxidation Furnace
O
2
, H
2
, N
2
, Cl
Flow rate
Exhaust
Temperature
Temperature profile
Time
Inspection
Film thickness
Uniformity
Particles
Defects
Figure 10.23

Process Recipe for Dry Oxidation Process
Step
Time
(min)
Temp
(C)
N
2
Purge
Gas
(slm)
Process Gas
N
2
O
2
HCl
(slm) (slm) (sccm)
Comments
0 850 8.0 0 0 0 Idle condition
1 5 850 8.0 0 0 Load furnace tube
2 7.5
Ramp
20C/min
8.0 0 0
Ramp temperature up
3 5 1000 8.0 0 0
Temperature
stabilization
4 30 1000 0 2.5 67 Dry oxidation
5 30 1000 8.0 0 0 Anneal
6 30
Ramp
-5C/min
8.0 0 0
Ramp temperature
down
7 5 850 8.0 0 0 Unload furnace tube
8 850 8.0 0 0 0 Idle
Note: gas flow units are slm (standard liters per minute) and sccm (standard cubic centimeters per minute)
Table 10.6

Wafer Loading Pattern in Vertical Furnace
160
1
4 Filler (dummy) wafers
4 Filler (dummy) wafers
1 Test wafer
1 Test wafer
1 Test wafer
75 Production
wafers
75 Production
wafers
Calibration parameters:
Boat size: 160 wafers
Boat pitch: 0.14 inch
Wafer size: 8 inches
Elevator speed: 9.29 cm/min
Cool down delay: 20 minutes
Figure 10.24


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2001 by Prentice Hall Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

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