Frequency Divider

Introduction
This brief article describes a frequency divider with
VHDL along with the process to calculate the scaling
factor.
The scaling factor
The frequency divider is a simple component which
objective is to reduce the input frequency. The
component is implemented through the use of the
scaling factor and a counter. The scaling factor is the
relation between the input frequency and the desired
output frequency:






Assuming an input frequency of 50MHz and
provided we need an output frequency
of 200Hz, we yield:



Therefore, the counter of the frequency
divider generates the output signal
of 200Hz each 250000 cycles.

The code Clock Divider


frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 124999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

The frequency_divider process,generates the
200Hz signal by using a counter from 1 to
124999. Why 124999 and not 250000? A clock
signal is a square wave with a 50% of duty cycle
(same time active and inactive); for this case,
125000 cycles active and 125000 cycles inactive.
Since the counter begins at zero, the superior
limit is 125000 - 1.

The reset signal is an essential part in any digital
system and its function in this component is to
restart the counter
Finite State Machines
Sequential circuits
primitive sequential elements
combinational logic
Models for representing sequential circuits
finite-state machines (Moore and Mealy)
Basic sequential circuits revisited
shift registers
counters
Design procedure
state diagrams
state transition table
next state functions
Hardware description languages


Finite state machine representations
States: determined by possible values in sequential storage elements
Transitions: change of state
Clock: controls when state can change by controlling storage elements

Sequential logic
sequences through a series of states
based on sequence of values on input signals
clock period defines elements of sequence

Counters are simple finite state
machines
Counters
proceed through well-defined sequence of states in response to enable
Many types of counters: binary, BCD, Gray-code
3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...




How do we turn a state diagram into
logic?
Counter
3 flip-flops to hold state
logic to compute next state
clock signal controls when flip-flop memory can change
wait long enough for combinational logic to compute new value
don't wait too long as that is low performance

D Q D Q D Q
OUT1 OUT2 OUT3
CLK
"1"
FPGA Vs Microcontroller
FPGAs are going to rule in the future because
of their flexibility, increasingly better power
efficiency and decreasing prices.

FPGAs are concurrent while the
microcontroller as always sequential.
This makes FPGAs better suited for real-time
applications such as executing DSP algorithms.
FPGA are flexible, you can add subtract the
functionality as required. This can not be done in
microcontroller.
The development time in case of conventional
microcontroller is shorter and that of FPGA takes
time because you need to glue-
up different modules yourself and test them to
perfection before doing anything.
Microcontroller, up-til now, are power efficient.
Microcontroller are low-cost, much lower than
FPGAs. This is specially true for small applications
and large quantities.
Microcontrollers are available in easy to solder