1

ARM
2
Introduction

Based on RISC technology
Advanced RISC Machines (ARM) was established
as a joint venture between Acorn, Apple in 1990
ARM is leading provider of 16/ 32-bit embedded
RISC microprocessor solutions
32 bit RISC processor of load/store architecture



3
ARM Evolution
4
ARM Evolution
From 1989-2000, 5 major version of ARM ISA are
V1 to V5
Version V1 and V2 supports
26 bit memory addressing
32 bit product multiply support
V3 introduced 32-bit addressing, and architecture
variants:
T Thumb state: 16-bit instruction execution.
M long multiply support (32 32 )
These features became standard in architecture V4 and
beyond.
ARMv3
5
ARMv4
Full 64 bit product multiply instruction as well
as 32 bit product multiply instructions plus load
and store instructions (16 bit)
E.g ARM 7
Improved ARM and Thumb interworking
architecture variants:
E enhanced DSP instructions including saturated
arithmetic operations and 16-bit multiply operations
J support for new Java state.
Specialized instruction for managing software debugging
E.g ARM 9, ARM10
ARMv5
6
ARMv6
All with T, M, E, and J extensions
More than 60 SIMD instructions
Improved Mixed-Endian Support
E.g, Little-Endian OS + Big-Endian Data
7
ARM Powered Products
8





Versions:
ARM7TDMI (3-stage)
ARMS, ARM9TDMI (5-stage)
ARM10TDMI ( 6-stage)

9
Pipeline Organization
3-stage pipeline: Fetch Decode - Execute
cycle
Fetch Decode Execute
Fetch Decode Execute
Fetch Decode Execute
i
n
s
t
r
u
c
ti
o
n
t t+1 t+2 t+3 t+4
i
i+1
i+2
10
Write-back
Buffer/data
Execute
Decode
Pipeline Organization
Stages:
Fetch
11
INTRODUCTION TO PHILIPS
LPC21xx

It is based on a 16/32 bit ARM7TDMI
It provides large buffer size and high processing
power.
Voltage supply 1.8V/3.3V and single supply






12
13



Device ----- LPC2138
Number of pins ------ 64
On-chip SRAM ------- 32 kB
On-chip FLASH------- 512 Kb
Number of 10-bit ADC
Channels --- 16
Number of 10-bit DAC
channels --- 1


Device information
14
ARCHITECTURE
15

Architectural overview
The ARM7TDMI-S is a general purpose 32-bit core which
offers high performance and very low power consumption.
The ARM7TDMI-S processor has two instruction sets
1) The standard 32-bit ARM set.
2) A 16-bit Thumb set.








16
Interrupt controller


The VIC accepts all of the interrupt request inputs and
categorizes them as FIQ , vectored IRQ, and non-
vectored IRQ as defined by programmable settings

1)Fast Interrupt request (FIQ) has the highest priority.

2) Vectored IRQs have the middle priority.

3) Non-vectored IRQs have the lowest priority



17
Brown Out detector
The 2138 include monitoring of the voltage on
the VDD pins.
If this voltage falls below 2.9 V, the BOD
asserts an interrupt signal to the Vectored
Interrupt Controller.
18
Reset and wake-up timer

Reset has two sources on the LPC2138: the
RESET pin and watchdog reset.


The wake-up timer ensures that the oscillator
and other analog functions required for chip
operation are fully functional before the
processor is allowed to execute instructions.

The wake-up timer monitors the crystal
oscillator as the means of checking whether it
is safe to begin code execution.
19


The purpose of the watchdog is to reset the
microcontroller within a reasonable amount
of time if it enters an erroneous state.

Watchdog timer

Crystal oscillator
On-chip integrated oscillator operates with
external crystal in range of 1 MHz to 30 MHz
20
Pulse Width Modulator (PWM)
The PWM is based on the standard Timer
Pin description
Pin

Type

Description
PWM1

Output

Output from PWM channel 1.

PWM2 Output

Output from PWM channel 2.
PWM3 Output

Output from PWM channel 3
PWM4 Output

Output from PWM channel 4
PWM5 Output

Output from PWM channel 5
PWM6 Output

Output from PWM channel 6.
21
10-bit A/D converter

Two 10-Bit Successive Approximation
ADCs, 8 channels each
Measurement range of 0 V to 3.3 V.





22
Analog-to-Digital Converter (ADC)
Pin description
Pin

Type Description

AD0.7:0
&
AD1.7:0

Input

Analog Inputs. The ADC cell can measure the
voltage on any of these input signals.

VREF

Reference

Voltage Reference. This pin is provides a
voltage reference level for the A/D converter(s).

VDDA, VSSA

Power

Analog Power and Ground. These should be
nominally the same voltages as VDD and VSS,
but should be isolated to minimize noise and
error.

23
Register description
Generic
Name

Description

Access

ADCR

A/D Control Register. The ADCR register must be
written to select the operating mode before A/D
conversion can occur.

R/W

ADGDR

A/D Global Data Register. This register contains the
ADCs DONE bit and the result of the most recent
A/D conversion.

R/W

ADSTAT

A/D Status Register. This register contains DONE and
OVERRUN flags for all of the A/D channels, as well as
the A/D interrupt flag.

RO

ADGSR

A/D Global Start Register. This address can be written
to start conversions in both A/D converters
simultaneously.

WO

24
ADINTE
N

A/D Interrupt Enable Register. This register contains
enable bits

ADDR0

A/D Channel 0 Data Register. This register
contains the result of the most recent conversion
completed on channel 0.

ADDR1

A/D Channel 1 Data Register. This register
contains the result of the most recent conversion
completed on channel

ADDR2,3,
4,5,6,7
SAME DESCRIPTION
25
10-bit D/A converter


10-bit resolution DAC with a buffered output
Based on resistor string architecture
Selectable Conversion speed vs power
Power down mode









26
Digital-to-Analog Converter (DAC)
Pin description
Pin

Type

Description

AOUT

Output

Analog Output. After the selected settling time
after the DACR is
written with a new value, the voltage on this pin
(with respect to
VSSA) is VALUE/1024 VREF.

VREF

Reference

Voltage Reference. This pin provides a voltage
reference level for
the D/A converter.

VDDA,
VSSA

Power

Analog Power and Ground. These should be
nominally the same
voltages as V3 and VSSD, but should be isolated to
minimize noise
and error.

27
DAC Register
This read/write register includes the digital value to be converted to
analog, and a bit that trades off performance vs. power. Bits 5:0 are
reserved for future, higher-resolution D/A converters.
Bit

Symbol

Value

Description

5:0

Reserved, user software should not
write ones to reserved bits. The value
read from a reserved bit is not defined.

15:6

VALU
E

After the selected settling time after
this field is written with a new VALUE,
the voltage on the AOUT pin (with
respect to VSSA) is VALUE/1024
VREF.

28
16

BIAS

0

1
The settling time of the DAC is 1 s
max, and the maximum current is 700
A.
The settling time of the DAC is 2.5
s and the maximum current is 350
A.

31:17 -

Reserved, user software should not
write ones to reserved bits.
The value read from a reserved bit is
not defined.

Bits 19:18 of the PINSEL1 register (PINSEL1 - 0xE002 C004) control whether
the DAC is enabled and controlling the state of pin P0.25/AD0.4/AOUT.
29
General purpose parallel I/O

Device pins that are not connected to a
specific peripheral function are controlled by
the GPIO registers.
Direction control of individual bits is set
using IODIR register.
Separate control of output set and clear.



30
Pin connect block
The pin connect block allows selected
pins of the microcontroller to have
more than one function. Configuration
registers control the multiplexers to
allow connection between the pin and
the on chip peripherals.
31
PINSEL0 - 0xE002C000

The PINSEL0 register
controls the functions of
the pins as per the
settings listed
The direction control bit
in the IODIR register is
effective only when the
GPIO function is
selected for a pin.

32
PINSEL0 - 0xE002C000
33
PINSEL1 - 0xE002C004

34
PINSEL1 - 0xE002C004

35
PINSEL2 - 0xE002C014

36
General Purpose Input/Output ports (GPIO)
Pin description
Pin

Input/
Output

Description
P0.0-P.31
P1.16-P1.31

Input/
Output

General purpose input/output. The number of
GPIOs actually available depends on the use of
alternate functions.

( 48 GPIO)
LPC213x has two 32-bit General Purpose I/O ports.
PORT1 has up to 16 pins available for GPIO functions.
PORT0 and PORT1 are controlled via two groups of 4 registers
IOPIN, IOSET, IODIR, IOCLR

37
GPIO register map (legacy APB accessible registers)
Pin Description Access
IOPIN

GPIO Port Pin value register. The current state of the GPIO
configured port pins can always be read from this reg, regardless of
pin direction.

R/W

IOSET
(IO0SET,
IO1SET)
GPIO Port Output Set register. This register controls the state of
output pins in conjunction with the IOCLR register. Writing 1s
produces highs at the corresponding port pins. Writing zeroes has no
effect.

R/W
IODIR
(IO0DIR,
IO1DIR)
GPIO Port Direction control register. This register individually
controls the direction of each port pin.
0 Input
1 output
R/W
IOCLR
(IO1CLR,
IO1CLR)

GPIO Port Output Clear register. This register controls the state of
output pin.writing 1s produces low & clears bit in the IOSET reg.
Writing 0s has no effect.

W/O
38
/*SquareWave.c This program will produce a square wave of approximately 1 KHz on Pin 3 of connector JP3. It is timed using adelay
loop. */
#include <Philips\LPC2138.h>
#define CRYSTAL_FREQUENCY_IN_HZ 14745600
#define PLL_MULTIPLIER 1
#define DEL_LOOPS CRYSTAL_FREQUENCY_IN_HZ*PLL_MULTIPLIER/86172
#define PIN 0x00008000 // P0.15 = IO_A pin 1
#define IODIR IO0DIR // using P0 (IODIR: 1=out, 0=in)
#define IONDIR IO1DIR // whatever port isn't used
#define IOCLR IO0CLR
#define IOSET IO0SET
void delay() { unsigned i;
for (i=0; i<DEL_LOOPS; i++) {} }
void main ( )
{ PINSEL0=0; // PINSEL(0,1,2) = 0 configures pins as GPIO
PINSEL1=0; // (probably not necessary: PINSELs default to zero)
PINSEL2=0; // except P0.24, which doesn't exist on LPC2138
IODIR=PIN; // only our output pin will be configured as output
IONDIR=0;
for(;;) {
IOCLR=PIN;
delay();
IOSET=PIN;
delay(); }}
39



The LPC2138 contain two UARTs.
(UART0 and UART1)
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator.

UARTs

40

UART0 & UART1
Pin description
Pin Type Description
RXD0

Input

Serial Input. Serial receive data.

TXD0 Output Serial Output. Serial transmit data.

Register description
Name

Description

Access

U0RBR

Receiver Buffer Register

RO
U0THR

Transmit Holding Register

WO
41
I2C-bus serial I/O controller

The LPC2138 contain two I2C-bus controllers.
The I2C-bus is bi-directional
The inter-IC control using only two wires
1) A serial clock line (SCL)
2) A serial data line (SDA).
3) The I2C-bus implemented in LPC2138 supports bit
rates up to 400 kbit/s (Fast I2C).



42
I2C interfaces I2C0 and I2C1
Pin description
Pin Type Description
SDA0,1

Input/Output

I2C Serial Data.

SCL0,1

Input/Output

I2C Serial Clock.

43
General purpose timers/external event
counters

It consist of 2 timer
A 32-bit Timer/Counter with a programmable
32-bit Prescaler.



44
ARM Instruction Set
45
Instruction Set
Two instruction sets:
ARM
Standard 32-bit instruction set
THUMB
16-bit compressed form
Code density better than most CISC
46
ARM Instruction Set
Features:
All instructions are 32 bits long.
Load/Store architecture
Conditional execution
Shift & ALU operation in single clock cycle
Most instructions execute in a single cycle.

47
ARM Instruction Set
Conditional execution:
Each data processing instruction
prefixed by condition code
Result smooth flow of instructions through pipeline
16 condition codes:
EQ equal MI negative HI unsigned higher GT
signed greater
than
NE not equal PL positive or zero LS
unsigned lower
or same
LE
signed less than
or equal
CS
unsigned
higher or same
VS overflow GE
signed greater
than or equal
AL always
CC unsigned lower VC no overflow LT signed less than NV special purpose
48
ARM Instruction Set
ARM instruction set
Data processing
instructions
Data transfer
instructions
Software interrupt
instructions
Block transfer
instructions
Multiply instructions
Branching instructions
49
Data Processing Instructions
Arithmetic operations:
ADD, ADC, SUB, SBC, RSB, RSC
Bit-wise logical operations:
AND, EOR, ORR, BIC
Register movement operations:
MOV, MVN
Comparison operations:
TST, TEQ, CMP, CMN
3-address format:
Two 32-bit operands
(op1 is register, op2 is register or immediate)


Remember, this is a load / store architecture
These instruction only work on registers, NOT memory.
Arithmetic Operations
Operations are:
ADD operand1 + operand2
ADC operand1 + operand2 + carry
SUB operand1 - operand2
SBC operand1 - operand2 + carry -1
RSB operand2 - operand1
RSC operand2 - operand1 + carry - 1
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Examples
ADD r0, r1, r2
SUBGT r3, r3, #1
RSBLES r4, r5, #5
Comparisons
The only effect of the comparisons is to
UPDATE THE CONDITION FLAGS. Thus no need to
set S bit.
Operations are:
CMP operand1 - operand2, but result not written
CMN operand1 + operand2, but result not written
TST operand1 AND operand2, but result not written
TEQ operand1 EOR operand2, but result not written
Syntax:
<Operation>{<cond>} Rn, Operand2
Examples:
CMP r0, r1
TSTEQ r2, #5
Logical Operations
Operations are:
AND operand1 AND operand2
EOR operand1 EOR operand2
ORR operand1 OR operand2
BIC operand1 AND NOT operand2 [ie bit clear]
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Examples:
AND r0, r1, r2
BICEQ r2, r3, #7
EORS r1,r3,r0
Data Movement
Operations are:
MOV operand2
MVN NOT operand2
Note that these make no use of operand1.
Syntax:
<Operation>{<cond>}{S} Rd, Operand2
Examples:
MOV r0, r1
MOVS r2, #10
MVNEQ r1,#0
54
Data Transfer Instructions
Load/store instructions
Used to move signed and unsigned
Word, Half Word and Byte to and from registers

LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRSH Load Signed Half Word STRSH Store Signed Half Word
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte STRSB Store Signed Byte
55
Block Transfer Instructions
Load/Store Multiple instructions
(LDM/STM)
Whole register bank or a subset
copied to memory or restored
with single instruction
R0
R1
R2
R14
R15
M
i

M
i+1
M
i+2
M
i+14
M
i+15
LDM
STM
56
Branching Instructions
Branch : B{<cond>} label
Branch with Link : BL{<cond>}sub_routine_label

Branch exchange (BX) and
Branch link exchange (BLX):
57
Thumb Instruction Set
Compressed form of ARM
Instructions stored as 16-bit,
Decompressed into ARM instructions and Executed
Lower performance (ARM 40% faster)
Higher density (THUMB saves 30% space)
58
THUMB Instruction Set
More traditional:
No condition codes
Two-address data processing instructions
Access to R0 R8 restricted to
MOV, ADD, CMP
Maximum 255 SWI calls