Die Recognition

Die Circuit Recognition
and Basic Logic Circuit Operation

Training for Engineers
May 12, 2005
IC Device Recognition
Course Objectives:
The Objectives of this course are to enable the attendees:
To explain the basic concepts of CMOS process and

fabrication steps.
To recognize and familiarize

components/elements in die level.
To illustrate how transistors and basic logic gates work.
with
electronics
Course Outline:
Basic IC Fabrication Process

Introduction to Fabrication
Silicon Wafer Preparation
Silicon Planar Technology
Identification of bipolar and MOS transistors,
resistors, capacitors and Diodes.
IDT Samples
Basic Logic Gates Operation
I. Fabrication Process:
Introduction to Fabrication
Silicon Wafer Preparation

Oxidation
Photolithography
Doping
Metallization/Aluminum
Patterning Process
MOSFET Formation
Introduction to Fabrication:
Integrated circuits are fabricated on thin circuit slices of

silicon called wafers. Each wafer contains several individual
chips or die (see figure below). For production purposes
each die on a wafer is usually identical.
A die on the silicon wafer

Top view
Side view
Wafer diameter is typically 5 to 8 inches.
Silicon Wafer Preparation:
Starting material of a semiconductor grade

polycrystalline silicon.
Uses Czochralski (or float-zone) method to
produce P type (or N type) single crystal silicon
ingots.
Ingots are sliced to wafers, lapped and then

polished.
Example of an ingot slicer.

Example of a Czochralski Silicon

Crystal Growing Furnace.
Silicon Planar Technology:
Oxidation
Photolithography
Doping
Metallization
These four basic techniques came together and made IC

manufacture possible.
A modern IC process is not simple. One objective of the
short course is to more or less understand a complete
CMOS process.
Oxidation:
The reaction of the silicon atoms to the oxygen

atoms forming Silicon Dioxide (SiO2)
For short, people usually call it oxide.
The oxide is a thin film for photolithography.
The oxide is a glass, similar to window glass.
Types of Thermal Oxidation
Dry Oxidation is done a furnace, red hot.
Wet Oxidation is done with water vapor.
Photolithography:
Photolithography on silicon wafers is very similar to

photolithography on PC boards. But everything is
reduced to smaller dimensions.
In addition to making wires, electronic components
are also made on the wafer.
The oxide is used as a mask:
10
Photolithography:
The means by which microscopically small circuit and device

patterns can be produced on the silicon wafer.
Steps include:
Photoresist application
Prebake
Alignment and exposure
Development
Postbake
Oxide etching
Photoresist stripping
11
Development:
Negative Photoresist
Photomask
Photoresist
SiO2
Substrate
Positive Photoresist
Photoresist
SiO2
Substrate
12
Oxide Masking
Mask pattern plan

Chrome on glass mask
Photoresist
Oxide
Wafer after develop cross section
Wafer after etch and photoresist strip
13
Doping:
There are two kinds of semiconducting silicon:

P type silicon carriers positive electricity.
N type silicon carriers negative electricity.
Silicon is made p type or n type by adding impurities. This
is called doping.
Dopants can be added when the silicon wafer is made.

Dopants can be added in a furnace; This is called
diffusion.
Dopants can be added by shooting ionized atoms into
wafer; this is called ion implantation.
14
Interstitial Diffusion:
Interstitial diffusant
Silicon atoms
15
Substitutional Diffusion:
16
Ion Implantation:
Bombardment of high-energy dopant ions in the

silicon surface.
Used to produce a shallow surface region of dopant
atoms deposited into the wafer.
Can be used as an alternative to deposition diffusion.
More precise control over the dopants on the silicon
surface.
17
Ion Implantation:
Consider a wafer made with Phosphorus in it;
Phosphorous makes silicon n type
Next, lets use ion implantation to add Boron;
Boron makes silicon p type.
Transistors and other electronic components are made
by putting together small n type and p type regions.
Boron ions
Oxide
p-Si
n-Si
18
Metallization/Aluminum:
Process to produce thin-film metal interconnect

between devices and circuit elements on the wafer.
The aluminum is used for wires just like the copper
on PC boards.
19
Patterning Process:
Integrated circuits are formed by patterning different layers on

and in the CMOS wafer. Consider the following sequence of
events that apply in a fundamental way, to any layer we need to
pattern. We start out with a clean, bare wafer shown below.
For cross section cut

along dotted line
p-type substrate
(b) Cross-sectional view of (a)
(a) Unprocessed wafer

20
Patterning Process:
First step in patterning is to grow an oxide, SiO2 or glass, a very

good insulator. Simply exposing the wafer to air yields the
reaction Si + O2 SiO2. The grown rate increases temperature.
The next step is to deposit a photosensitive resist layer across
the wafer shown below.
A
A
Oxide
p-type substrate
p-type substrate
(d) Deposit photoresist
(c) Grow gate oxide (SiO2)

21
Photoresist
Oxide
Patterning Process:
After the resist is baked, the mask derived from layout program,
Figure (e) is used to selectively illuminate areas of the wafer.
The light passing through the opening in the reticle is
photographically reduced to illuminate the correct size area on
the wafer.
A
Mask(reticle)
Mask(reticle)
Photoresist
Oxide
Photoresist
Oxide
p-type substrate
p-type substrate
(e) Placement of the mask

over the wafer.
(f) Exposing photoresist.

22
Patterning Process:
The photoresist is developed, removing the areas that were

illustrated. This process is called a positive resist process
because the area that was illustrated was removed. Then remove
the exposed oxide areas. Notice that the etchant etches under
the resist, causing the opening in the oxide that was specified by
the mask.
Photoresist
Oxide
Photoresist
Oxide
p-type substrate
p-type substrate
(g) Developing exposed

photoresist.
(h) Etching oxide to

expose wafer
23
Patterning Process:
The final and last step in the patterning process is to remove the
resist. Figure (i) shows the cross-sectional view of the opening
after the resist has been removed.
Oxide
p-type substrate
(i) Etching oxide to expose

wafer.
24
Patterning the N-well:

We can make an n-well by diffusing donor atoms, those
with 5 valence electrons, as compared to 4 for silicon, into
the wafer.
Deposit a layer of resist directly on the wafer without
oxide.
Expose the resist to light through a mask and
developing or removing the resist.
Expose the wafer to donor atoms.
After a certain amount of time, the diffusion source is
removed.
The final step is the removal of the resist.
25
Laying Out the N-well:
Diffusion of donor atoms

Resist
p-type substrate
Start of diffusion into the wafer
(j) Diffusion of donors atoms

Resist
n-well
p-type substrate
n-well
(k) After diffusion

n-well
n-well
n-well
p-type substrate
p-type substrate
(l) After resist diffusion

26
(m) Angel view of n-well
MOSFET Formation:
A
B
n-well
For cross section cut

along dotted line
(a) Wafer with n-well defined.

defined by n+ mask
A
(b) Cross-sectional view of (a).
defined by n-well
B
n-well
n-well
p-type
p-type
(c) Define n+ and n-well areas and

grow thin/stress relief oxide.
p-type
(d) Deposit nitride over

stress relief oxide.
27
MOSFET Formation:
n-well
n-well
FOX
p+ implant
p-type
p-type
(f) Growth of the field oxide.
(e) Implant of p+ in field region.
Poly1
n-well
n-well
Gate Oxide
p-type
p-type
(g) Growth of the field oxide.

(h) Deposit gate oxide and poly.

28
MOSFET Formation:
n-channel MOSFET
N+
N+
p-channel MOSFET
N+
n-well
N+
P+
P+
n-well
n+ active areas
source and drain areas
p-type
p-type
(i) Implant n+ source and drain regions
N+
(j) Implant p+ source and drain regions
N+
P+
P+
n-type Well
p-type substrate
(k) Deposit aluminum contact.

29
MOSFET Formation:
(l) CMOS inverter cross-section.

30
MOSFET Formation:
(m) CMOS inverter composite layout.
(n) CMOS inverter electrical diagram.

31
II. Device Identification:
Bipolar
FET
Gates
Resistors
Capacitors
Bondpad
ESD
32
Bipolar:
Bipolar Fabrication Steps
Different Types of Bipolar Transistors

NPN
Basic Vertical NPN
Magnified Emitter NPN
Multiple Emitter NPN
Power NPN
PNP
Basic Lateral PNP
Multiple Emitter PNP
Multiple Collector PNP
Substrate/Vertical PNP
33
Bipolar Fabrication Steps
C
NPN
E
PNP
FABRICATION STAGES
E
Starting material, P-type substrate

LAYOUT GEOMETRY
N-type Buried Layer Diffusion
Grow Si02
Apply Photoresist
Expose through Mask
Develop and Remove Photoresist
Etch Si02
Predeposition and Diffusion
Epitaxial Growth
Isolation Diffusion
Base (P+) Diffusion
P+
P+
CROSS SECTION
Emit (N+) Diffusion

Contact Opening
Metal Deposition/Etching
N+
P- Iso
P+
N+
P- Iso
N+ Buried Layer
N+ Buried Layer
P+
N+ Buried Layer
N+ Buried Layer
P-SUB
N+
P- Iso
Basic NPN Die Image:

C
B
E
E
E
E
E
35
Different Types of NPN

Power NPN
Basic NPN
EA = 24
EA = 1
Magnified Emitter NPN
Multiple Emitter NPN
EA = 3
EA = 1
Magnified Emitter NPN Die Image:
B
E
B
E
37
Different Types of Lateral PNP

Basic PNP
Multiple Emitter PNP
Multiple Collector PNP
E
B
B
B
C
C
Lateral PNP Die Image:
E
E
B
E
C
39
Substrate/Vertical PNP
SYMBOL
LAYOUT GEOMETRY
FAB STAGES
CROSS SECTION

Epitaxial Growth
Isolation Diffusion
Base (P+) Diffusion
P+
N+
P+
N+
P-ISO
Emit (N+) Diffusion

Contact Opening
P-ISO
N-EPI
P-SUB
Field Effect Transistor (FET):
MOSFET Fabrication Steps
MOSFET Structure
Basic
Series
Parallel
Different Types of FETS
NMOS
PMOS
41
MOSFET Fabrication Steps

G
FAB STAGES
NMOS
S
PMOS
N-well Diffusion
LAYOUT GEOMETRY
Nitride Deposition
Field Oxidation
S
Polysilicon Deposition
N-Channel Diffusion
P-Channel Diffusion
CROSS SECTION
Contact Opening
N+
N+
P+
P+
n-type Well
p-type substrate
MOSFET Structures
SINGLE
PARALLEL
B
A
SERIES
A
A
B
N-channel MOSFET Die Image:
S
D
G
drain
N+
D
G
source
N+
bulk
P+
guard
ring
P-sub
gate
44
P-channel MOSFET Die Image:
G
S
D
gate
B
drain
P+
P-sub
B
D
P+
N-well
S
G
source
45
bulk
N+
guard
ring
MOSFET Characteristics:
It should be noted that there is no physical difference

between the drain and the source.
The source terminal of an NMOS is defined as
whichever the two terminals has a lower voltage.
The source terminal of an PMOS is defined as
whichever of the two terminals has a higher voltage.
PMOS is generally larger than NMOS.
PMOS is located near at VDD, while, NMOS is located
near at VSS.
46
Universal Logic Gates:
Inverter
NAND Gate
NOR Gate
Transmission Gate
47
Logic Gates Layout

IN
INVERTER
Acrtive Region
OUT
NAND
A
B
N+
Polysilicon
VCC
IN
IN OUT
OUT
Metal
VCC
VCC
VCC
P+
B
X
B
GND
GND
GND
GND
TRANSMISSION GATE
NOR
CB
IN
A
B
X
VCC
VCC
OUT
CB
C
B
IN
OUT
CB
IN
A
A
OUT
GND
C
GND
Inverter Die Image:

In
Vdd
In
Out
Vdd
In
Vdd
In
Out
Out
D. Schematic Symbol
Vss
Vss
A. Die Image
B. Layout Diagram
In
Vss
P+
N+
F. Cross-sectional Diagram
C. Schematic Ckt
49
Out
Vdd
P+
P-sub
In
E. Truth Table
Out
N+
Out
P+
N-well
N+
NAND Gate Die Image:
Vdd
Vdd
A
B
B
Vdd
Vss
C. Schematic Ckt
D. Schematic Symbol
Vss
A
A. Die Image
Vss
B. Layout Diagram
50
E. Truth Table
NOR Gate Image:

A
Vdd
B
Vdd
X
A
Vss
A
B
Vss
Vss
A. Die Image
Vdd
C. Schematic Ckt
D. Schematic Symbol
B
B. Layout Diagram
51
E. Truth Table
Resistors:
Diffused Resistor (Base Diffusion)
Base Pinched Resistor

Epitaxial Layer Resistor
Pinched Epitaxial Layer Resistor
Ion-Implanted Resistor
Thin-Film Resistor
52
Resistance:
R = L = L
A
tW
where:
= average resistivity of the layer

L = length
t = layer thickness
W = width of the layer
53
Diffused Resistor (Base Diffusion):
SiO2
P+ (200 /SQUARE
P+
P+
N-TYPE EXPITAXIAL LAYER
P-TYPE SUBSTRATE
54
Base Resistor Die Image:
P-ISO
P+
P-ISO
N-EPI
P-SUB
55
Pinched Base Diffusion Resistor:
SiO2
N+
P+
P+
P+
(2-10 k/square)
P-TYPE SUBSTRATE
56
P+
Epitaxial Layer Resistor:
SiO2
N+
P+
N+
N-TYPE EPITAXIAL LAYER
(1-10 k/square)
P-TYPE SUBSTRATE
57
P+
Pinched Epitaxial Layer Resistor:
SiO2
N+
P+
P+
(2-10 k/square)
P-TYPE SUBSTRATE
58
N+
P+
Ion-Implanted Resistor:
SiO2
P+
P+
P+
P+
P-TYPE SUBSTRATE
Ion implanted (boron) later
(500-20 k/square)
59
Thin-Film Resistor:
Thin film
SiO2
(Ta, Nichrome, SnO2, etc.)
Silicon substrate
60
Thin-Film Resistor Die Image:
Thin Film
(Ta, Nichrome, Sn02, etc.)
Si02
Substrate
61
IC Resistor Characteristic:
62
Resistor Fabrication Steps
FAB STAGES
LAYOUT GEOMETRY

Epitaxial Growth
Isolation Diffusion
Epitaxial Layer
CROSS SECTION
Base (P+) Diffusion
Pinched Epitaxial Layer
Emit (N+) Diffusion

Ion Implantation
P-ISO
N+
N+
P-ISO
N+
P+
Thin Film Deposition
N+
P-ISO
N-EPI
Contact Opening
P-SUB
LAYOUT GEOMETRY
Base Diffusion
Pinched Base Diffusion
Ion-Implanted
Thin-Film
CROSS SECTION
P-ISO
P+
P+ N+
P+
N-EPI
P-SUB
P+
N+
P-ISO
Capacitors:
Collector-Base Junction Capacitor

Emitter-Base Junction Capacitor
Collector-Substrate Capacitance
Metal-Oxide-Silicon (MOS) Capacitor
Thin-Film Capacitor
64
Capacitance:
C= A
W
where:
= permitivity of silicon
A
A = junction area
W = dielectric width
65
Collector-Base Junction Capacitor:
SiO2
P+
N+
P+
N
N+
P-TYPE SUBSTRATE
66
P+
Emitter-Base Junction Capacitor:
SiO2
N+
P+
P+
P+
N+
P-TYPE SUBSTRATE
67
Emitter-Base Junction Capacitor:
P-ISO
N+
P+
P-ISO
N-EPI
P-SUB
68
Collector-Substrate Capacitance:
SiO2
N+
P+
P+
N+
P-TYPE SUBSTRATE
69
Metal-Oxide Silicon Capacitor:
Metal film
SiO2
N+
P+
P+
P-TYPE SUBSTRATE
70
Metal-Oxide-Silicon (MOS) Capacitor:
Metal Film
N+
P-ISO
P-ISO
N-EPI
P-SUB
71
Thin-Film Capacitor:
Dielectric
(SiO2, Si3N4, etc.)
Thin-film
Metal electrode
Silicon substrate
Thin film
Metal electrode
SiO2
72
Plate Capacitance:
73
Capacitors Fabrication Steps
FAB STAGES
LAYOUT GEOMETRY
N-type Buried Layer Diffusion
Epitaxial Growth
Isolation Diffusion
Collector-Base Junction
CROSS SECTION
Thin-Film
Base (P+) Diffusion

Emit (N+) Diffusion
Thin Film 1 Deposition
P-ISO
P+
N+
Thin Film 2 Deposition
P-ISO
N-EPI
Contact Opening
N Buried Layer
P-SUB
LAYOUT GEOMETRY
Emitter-Base Junction
Metal-Oxide-Silicon
Collector-Substrate
CROSS SECTION
P-ISO
P+
N+
N+
P-ISO
N-EPI
P-ISO
N+
P+
P-ISO
P-SUB
Bonding Pad:
Interface between the die and the lead frame.
Metal1
Metal2
Via
Pad Layer
Metal2
Metal1
Insulator
Insulator
Insulator
75
ESD Diode:
P+
Diode made using

the n-well/p+
N+
VCC
PAD
PAD
A. Layout Diagram
P+
Diode made using

the subtrate/n+
N+
GND
N-WELL
C. Equiv Schematic Ckt.
P-SUB
B. Cross-sectional Diagram
76
III. IDT SAMPLES: CAPACITOR

2nd Metal
1ST Metal
B. 2nd Metal etched

A. Unetched
Poly Silicon
Gate
D
G
S
D. Equiv. Schem. Ckt.
S
77
G D
C. All Metal etched
III. IDT SAMPLES: RESISTOR
R2
R1
R4
R3
R6
R5
B. 2nd Metal etched

A. Unetched
R2
R1
R4
R3
R6
R5

C. All Metal etched

78
III. IDT SAMPLES: TRANSISTOR
2nd Metal
1ST Metal
A. Unetched
B. 2nd Metal etched
S
G
B
D

S
79
C. All Metal etched

D
III. IDT SAMPLES: ESD

VCC
S
G
B
D
M1
M1
M2
PAD
D
G
B
S
Unetched
2nd Metal etched
All Metal etched
80
M2
III. IDT SAMPLES: PAD
Unetched
2nd Metal etched
81
All Metal etched
IV. Basic Logic Gates Operation:
Switches
Passgate or Transmission Gate

Inverter
Clock Inverter
Multiplexer or Mux
Nand Gate
Nor Gate
Latches
Flip-Flips
82
Structure of NMOS Transistor:

D
Source
ID
Gate
Drain
Gate current is zero because

SiO2 act as insulating material.
ID = Drain Current
B
S
W
FOX
FOX
N+
N+
Field Oxide separates the

transistor from other transistors.
L
p-type substrate
Parasitic diode
The body/bulk of an NMOS transistor must be grounded or

connected to the lowest potential in order to maintain a reverse
bias between the PN junctions separating the drain and the
source.
83
Structure of PMOS Transistor:

S
Source
Gate
Drain
ID = Drain Current
B
ID
D
W
FOX
FOX
P+
N+
P+
N+
P+
P+
Field P+ implant increase

Vth of the MOSFET parasitic
transistor made by Polyover
FOX so it wont turn-on.
n-well
p-type substrate
Parasitic diode
For N-well process, PMOS transistor is fabricated in the well which also
serve as the substrate.
The body/N-well must be connected to the highest potential to
maintain a reversed PN junction.
84
NMOS Behavior at OFF state:

VG<<VTH, the transistor is said to
Operate in the sub-threshold region.
VG
B
+ +
N+
N+
+ P+
++ +
+++ +
+
+
+
+ + + + + + + + + + ++ + + + + ++ +
+ + +
+
+ + + ++ +
+ ++ ++ + + + +
+
+ + +
+
+ + + + + + + p-substrate
+
+
+ ++ ++++ +++ ++
Immobile Acceptor Ion

Depletion Region
Holes residing in
the P-substrate
For DC gate voltage below the threshold voltage, VTH, a back to

back diode exist between source and drain so essentially no
current flow. A very small leakage current does flow because a
reverse PN junction have, as defined in the equation:
ID=IS (e Vd/Vt 1)
85
Depletion Region:
N-type silicon has a number of mobile electrons, while p-type

silicon has a number of mobile holes.
Formation of a pn junction results in a depleted region at the
p-n interface. A depletion region is an area depleted of mobile
holes or electrons.
Anode
86
Cathode
NMOS Behavior at Sub-threshold:
Electric Field
VD
VG
+ +
N+
N+
+ P+
+
+
+
++ +
+
+
+ + + + + ++ + + + + ++ + +
++
+ + + +++
+ ++ ++ +
+
+ +++
+
+
+
+ ++ ++++ +++ ++
VG<VTH, increased Electric Field

pushes the holes away from the
gate forming a depletion region
beneath the gate.
Negative ion or Acceptor Ion
Depletion Layer
Holes residing in
the P-substrate
As VG increases, but still below VTH, a depletion region is formed

beneath the gate. The depletion region formed beneath the gate
now connects the depletion region at the drain and source.
87
NMOS Transistor as Capacitor:

Electric Field
Electrons
B
VD
VG
S
+ +
N+
N+
+
+
+
+
++ +
+
+
+ + + + + ++ + + + + + ++ +
++
+
+
+
+
+
+
+
+
+
Depletion + + + +
+ +++
+
+
+
Capacitance
+ ++ ++++ +++ ++
VG>VTH, the electric field

pushes the holes farther
away from the gate channel.
Oxide Capacitance
P+
N-type inverted
layer means from
p to n carrier
For VG>VTH, an inverted layer is formed across the channel (making it

possible for electron to flow if a potential is applied across the source
and drain.
If Vd=0, the induced channel is uniform across the source and drain.
This condition makes the transistor behaves like a capacitor. A
depletion capacitance is formed between the depletion layer and the
substrate.
88
NMOS Behavior at Triode Region:

Electric Field
Electrons
B
VDS
VGS
S
D D
+ +
P+
N+
N+
Depletion +
+
+
+
++ +
+
Layer
+
+ + + + + ++ + + + + + ++ +
++
+
+
+
+
+
+
+
+ + + +
+
+
+ +++
+
+
+
+ ++ ++++ +++ ++
VGS>VTH, the electric field

Immobile acceptor ions
Induced channel is
no longer uniform
With VDS=0, the induced channel is uniform across the source

and drain.
When VDS0 and is positively increased, electrons are now
attracted towards the drain creating a drift current from drain to
source called ID(drain current). In this situation, induced
channel is no longer uniform.
89
NMOS Behavior at Triode Region:

The condition VGS VTH and VDS VGS- VTH, transistor is said
to be in the triode or linear or the ohmic region because the
transistor behaves like a resistor.
EOXULINW
VDS2
ID = -------------- [ (VGS-VTH)VDS ------ ]
TOX L
2
Where:
ID is the drain saturation current of the transistor.
Eox is the dielectric constant of the SiO2 which is 35.1345 aF/um
ULIN is the mobility of the holes and electron in a PMOS and NMOS transistor respectively.
Tox is the thickness of the oxide
W is the width of the transistor
L is the length of the transistor
VGS is the voltage across the gate and the source
VT is the threshold voltage of the transistor
90
NMOS Behavior at Saturation Region:

Electric Field
Electrons
B
VDS
VGS
S
+ +
P+
N+
N+
Depletion +
+
+
+
++ +
+
Layer
+
+ + + + + ++ + + + + + ++ +
++
+
+
+
+
+
+
+
+ + + +
+
+
+ +++
+
+
+
+ ++ ++++ +++ ++
VGS>VTH, the electric field

Pinched off
Increasing VDS increases the current in the channel since more

electrons are attracted towards the drain terminal. When
VDS=VGS-VTH, the charge of the inversion layer is zero because
the electric field generated by VDS already attracted all the
electrons that used to connect the drain and the source. The
channel that used to connect the drain and source has
disappeared or pinched-off.
91

Electrons
B
VDS
VGS
S
+ +
P+
N+
N+
Depletion +
++ +
+ +
+
Layer
+
+
+ + + + ++ + + + + ++ ++ +
++
+
+
+
+
+
+
+
+ + + +
+
+
+ +++
+
+
+
+ ++ ++++ +++ ++

Pinched off point
Once the channel has piched-off, the voltage drop across it

becomes constant and the drain current is constant. The
transistor is in saturation.
As VDS is increased further, the pinch off point moves closer to

the source. A portion under the gate no longer has an inversion
layer underneath it.
92

When VGS > VTH, the voltage drop across the transistor becomes constant
and the drain current is constant. The transistor is said to be in saturation.
EOXULINW
ID = --------------- (VGS-VTH)2
2L
Where:
ID is the drain saturation current of the transistor.
Eox is the dielectric constant of the SiO2 which is 35.1345 aF/um
ULIN is the mobility of the holes and electron in a PMOS and NMOS transistor respectively.
Tox is the thickness of the oxide
W is the width of the transistor
L is the length of the transistor
VGS is the voltage across the gate and the source
VT is the threshold voltage of the transistor
93
Switches:
Open Circuit (Switch is OFF)

1. NMOS
G=0
VIN = 0V; VOUT = Z (High Impedance)

VOUT
VIN
VIN = VDD; VOUT = Z (High Impedance)
2. PMOS
G = VDD
VIN
VIN = 0V; VOUT = Z (High Impedance)

VOUT
94
VIN = VDD; VOUT = Z (High Impedance)
Switches:
Open Circuit (Switch is ON)

1. NMOS
G = VDD
VIN = 0V; VOUT = 0V

VOUT
VIN
VIN = VDD; VOUT = VDD-VTH
2. PMOS
G=0
VIN
VIN = 0V; VOUT = VTH

VOUT
95
VIN = VDD; VOUT = VDD
Transmission/Pass Gate:
Since the NMOS passes logic LOW well and PMOS passes logic
HIGH well, putting the two complementary MOS in parallel
results in a Passgate/Transmission Gate that passes both logic
level well.
CB
CB
IN
OUT
IN
OUT
C
96
In
Out
Inverter:
Inverter circuit is a combination of an NMOS and a PMOS in

series. Wherein, PMOS is connected at VDD or supply voltage
while NMOS is at the lower potential or ground side.
VCC
IN
IN
OUT
OUT
In
Out
VCC
IN
VCC
OUT
IN
OUT
GND
GND
97
GND
Clocked Inverter:
VCC
___
___
CK
CK
IN
OUT
IN
OUT
CK
CK
GND
98
Ck
In
Out
NAND gate:
VCC
A
OUT
A
OUT
GND
99
Out
NOR Gate:
VCC
A
OUT
A
OUT
B
GND
100
Out
Multiplier or Mux:
SB
A
A
OUT
OUT
B
B
SB
S
S
SB
101
Out
D-Latch:
QB
LB
D
QB
L
L
LB
LB
D
L
Q
102
D-Latch : w/ RESETBAR:
RB
QB
LB
Q
D
D
L
L
L
LB
LB
D
L
RB
Q
QB
RB
103
D-Latch : w/ RESET:
R
Q
LB
QB
D
D
L
L
LB
LB
D
L
Q
QB
R
104
D Flip-flops : Standard
CK
CKB
QB
D
CKB
CKB
CK
CK
CK
CK
CKB
CK
Q
105
QB
D Flip-flops: w/ RESET
R
CK
CKB
QB
D
CKB
CKB
CK
CK
CK
QB
R
CK
CKB
D
CK
RST
Q
106
D Flip-flops : w/ SETBAR
SB
Q
CK
CKB
QB
D
CKB
CKB
CK
CK
CK
CKB
D
CK
SB
Q
107
SB
D
CK
QB
D Flip-flops : w/ RESET & SETBAR

R
SB
Q
CK
CKB
QB
D
CKB
CKB
CK
CK
SB
D
CK
CKB
CK
QB
CK
SB
Q
108

Die Recognition

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Die Recognition

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Die Circuit Recognition

and Basic Logic Circuit Operation

The Objectives of this course are to enable the attendees:

To explain the basic concepts of CMOS process and

To recognize and familiarize

To illustrate how transistors and basic logic gates work.

Basic IC Fabrication Process

Silicon Wafer Preparation

Integrated circuits are fabricated on thin circuit slices of

A die on the silicon wafer

Silicon Wafer Preparation:

Starting material of a semiconductor grade

Ingots are sliced to wafers, lapped and then

Example of an ingot slicer.

Example of a Czochralski Silicon

Silicon Planar Technology:

Silicon Planar Technology

These four basic techniques came together and made IC

The reaction of the silicon atoms to the oxygen

Photolithography on silicon wafers is very similar to

The oxide is used as a mask:

The means by which microscopically small circuit and device

Mask pattern plan

Wafer after develop cross section

Wafer after etch and photoresist strip

There are two kinds of semiconducting silicon:

Dopants can be added when the silicon wafer is made.

Bombardment of high-energy dopant ions in the

Process to produce thin-film metal interconnect

Integrated circuits are formed by patterning different layers on

For cross section cut

(b) Cross-sectional view of (a)

(a) Unprocessed wafer

First step in patterning is to grow an oxide, SiO2 or glass, a very

(d) Deposit photoresist

(c) Grow gate oxide (SiO2)

(e) Placement of the mask

(f) Exposing photoresist.

The photoresist is developed, removing the areas that were

(g) Developing exposed

(h) Etching oxide to

(i) Etching oxide to expose

Patterning the N-well:

Laying Out the N-well:

Diffusion of donor atoms

Start of diffusion into the wafer

(j) Diffusion of donors atoms

(k) After diffusion

(l) After resist diffusion

(m) Angel view of n-well

For cross section cut

(a) Wafer with n-well defined.

(b) Cross-sectional view of (a).

(c) Define n+ and n-well areas and

(d) Deposit nitride over

(f) Growth of the field oxide.

(e) Implant of p+ in field region.

(g) Growth of the field oxide.

(h) Deposit gate oxide and poly.

(i) Implant n+ source and drain regions

(j) Implant p+ source and drain regions

(k) Deposit aluminum contact.

(l) CMOS inverter cross-section.

(m) CMOS inverter composite layout.