Flash ADC

Mixed Signal VLSI

Dr. Chris Hutchens
Xunyu Zhu

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Flash ADC
Outline
Introduction to the flash ADC structure
The challenges of high-speed flash ADC
applications

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Flash ADC
Flash ADC Block Diagram

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Flash ADC
The Comparator is Key
I2

I3

M3

M4

Vin

Vref

I4

Preamplifier

Regenerator
The schematic of comparator

Preamplifier buffering or isolation from the regenerator:

To minimize large sign kickback/flashback effect.
Preamplifier can be set low gain to work at high frequency.

Switches are an alternate choice.

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Flash ADC
Bubble Detector/Filter

Y An 1 An An 1

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Features
Error correction ability

Flash ADC
Tradeoff
Speed-power-accuracy tradeoff
The relationship between the speed, power, and accuracy for a Flash ADC is
given by [2],

Speed Accuracy 2
1

Power
Cox A2 vt
where, Avt is the Pelgrom process-dependent parameter(s).
From above it is shown that without extra precautions (topology),technology
scaling increases the power consumption.
Two at the architectural level [2]:
analog processing techniques (for example: folding interpolating)
averaging techniques - reduces the offset specification for high-speed
ADC without requiring larger transistors areas
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Both decreases input capacitance and number of preamplifiers or

comparators..

Flash ADC
Challenges
Input Capacitive loading
Resistor String Bowing
Signal and Clock Delay

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Flash ADC
Challenges
Input Capacitive Loading
The larger capacitance at the input- the lower the input frequency and increase the
power consumption.
The higher the n, the larger number of comparators.
Larger n demands smaller offset voltage at the input node- requires larger
transistor, and larger Cgs, [1].
The high bandwidth GBP. GBP=gm/CL, Keep the V constant, in order to get larger
GBP, larger transistor needed to get larger gm.
Solution:
Reducing the large capacitive loading, interpolating and averaging techniques will be
adopted.

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Flash ADC
Challenges
The restriction for Cgs:
Input signal loss error
Rg
Vinput

R1
Vinput M1

50
Cgs1

M2
Vsource

Cgs2

Vsource
R2
Cgs1

Cgs2
I1

Req

The schematic of preamplifier

Gain

Vinput
Vsource

1 Gain

The small-signal model of preamplifier

2 sReqC gs

2 s( Rg Req )Cgs

2 sRCgs 2n 1

2 s(50 R 2n 1 )C gs

LSB
4

Offset voltage

Vos
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1
LSB
W L 4

Where the A is process-related constant

Flash ADC
Challenges

Possible transfer responses for the

input-comparator output signals, V1
and V2, and their interpolated signals

( A ) ( A )
n ( A ) , n 1,2,3
4
n (4 n)
A
4
A max

Vnode

4-bit interpolating A/D converter (interpolating factor of 4)

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After interpolating, the maximum

offset is not change

Flash ADC
Challenges
Averaging architecture [3]

It works as following:
An array of differential pairs injects two
different types of stimuli currents into the
averaging network. First, the differential signal
currents Is(n) limited by the linear region of
the differential pair, enter the network. Second,
noise currents Ios(n) due to the transistor
random mismatches also enter the averaging
network. A well designed averaging network
should filter out the random currents without
losing the signal currents.

Offset averaging as spatial filtering

Optimum averaging network lowers random offset by up to 3 times 9 amps in the linear
region.
Accuracy is maintained with 9 times smaller FETs than if no averaging used.
9 times less capacitance possible and reduced power consuption.
With same bias current i.e. gm is 3X due to 3X Veff bandwidth is 3 times larger [4].
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Flash ADC
Challenges
Resistor String Bowing
Originally, bowing was observed in bipolar applications
Input currents of the bipolar comparators cause errors on the voltages of the nodes of
the resistor string.
In CMOS applications the bowing occurs at high frequencies.
R1

Cgs1

Vreference
M1

M2

Cgs2
Req

Vinput

Vinput
R2
Cgs1

Cgs2
I1

The small-signal model of preamplifier

Req R1 // R2

The schematic of preamplifier

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ReqMax R 2n 1
VerrorMax

ReqMax
LSB

1
4
2
ReqMax
s C gs

Flash ADC
Challenges
Signal and Clock Delay
Even very small differences in the clock or signal arrival at the different comparators
inputs results in errors.
Routing differences
capacitive loading
2A
Jitter.
LSB / 4
1
2n 4
t

A 2f

length

A 2f

2n 2 f

c / r
30cm
t

At 300 MHz and 12 bits

Where
f is the input signal frequency
A is the amplitude of the input signal
n is the number of ADC resolution bits
c is the velocity of the light
r is the relative electric permittivity

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Solution:
The clock and signals(s) should such that all delays matched. Signals delays do not need to
match clock delays. The exception being pipelined and interleaved ADCs.

Flash ADC
Challenges
Design Methodology
Given Inputs Number of bits, sampling rate (fn), Pellgrom numbers, noise models, KP,
Lambda effective, and parasitic Cs.
Estimate required Ws Differential Pair and Regenerator
Using Pellgrom numbers and Noise models
Using required C noise models and/or charge injection errors find gm and W
from fn
Select the greater Ws and estimate power consumption.
If not satisfied with the power consumption or bandwidth. Elect to use averaging or
interpolation or both.
Design an averaging amplifier that keeps eight or more amplifiers in the linear region. With 8
in the linear region one can reduce the area by 9X and the power or increase the BW by 3X as
well several combinations in between.

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Flash ADC
Reference
[1] M.J.M Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, Matching properties of MOS
transistor, IEEE J. Solid-State Circuits, vol. 24, pp.1433-1440, Oct. 1989.
[2] Koen Uyttenhove, M. Steyaert, Speed-Power-Accuracy Tradoff in high-speed CMOS
ADCs, IEEE trans. Circuit and Systems-II, vol.49, No.4, Apr. 2002.
[3] H. Pan, M. Segami, M. Choi, J. Cao, and A. A. Abidi, A 3.3V 12-b 50-MS/s A/D converter
in 0.6um CMOS with over 80dB SFDR, IEEE J. Solid-State Circuits, vol. 35, pp. 1769-1780,
Dec. 2000.
[4] M. Choi, and A. A. Abidi, A 6-b 1.3-Gsample/s A/D Converter in 0.35um CMOS, IEEE
J. Solid-State Circuits, vol 36, Dec. 2001.

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