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CT063-3.5-2
Prepared by: KNT First Prepared on: 31-1-14 Last Modified on: xx-xx-xx
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Copyright 2014 Asia Pacific University
What is a Register?
Types of Registers
Operations of Registers
Memory
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Learning Outcomes
At the end of the session you will be able to: describe a register
explain its operations
compare user visible registers (UVR) & user invisible
registers (UIR)
apply the idea of Status Flags for dynamic evaluation
of the ALU status.
calculate the current value of the PSW Register.
describe the type of memory
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CPU Architecture
The function of the CPU is to:
fetch instructions (from memory)
interpret instructions (decode them to determine
action)
fetch data (instruction execution may need operands
from memory)
process data (perform arithmetic operation)
write data (results are stored back in memory)
Register & Memory
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CPU Architecture
The CPU has three important parts: Control Unit - to fetch & decode instructions
ALU to perform arithmetic(*/+-) and logical operations
(and,or,not)
Registers to store temporary data
Another critical
aspect of CPU
architecture is
number and design
of registers
Control
Unit
ALU
CPU
High Speed Registers
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What is a Register?
Small, permanent storage locations within
the CPU used for a particular purpose.
Manipulated directly by the Control Unit.
Wired for specific function.
Size in bits or bytes (not MB like memory).
Can hold data, an address or an
instruction.
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Why Registers?
CPU must have some working space (temporary
storage)
CPU can't directly perform arithmetic in memory
E.g. if you want to add 1 to a memory location, the processor will
normally do this by loading the initial value from memory into a
register, adding 1 to the register, and then saving the value back
to memory.
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Why Registers?
Stores information about status of CPU and
currently executing program.
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Register Operations
1.
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Arithmetic Shift
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Register Operations
Registers are also used for:4. Testing contents for conditions such as
zero or positive.
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Register Organisation
A processor includes both
User Visible Registers
(UVR)
visible to programmer
may be general purpose
or have a special use
User Invisible Registers
(UIR)
used solely by the CPU
and special O/S
functions
are used to control the
operation of the CPU.
Register & Memory
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Register Organisation
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16bits
Accumulator
Base
Counter
Data
Base Pointer
Stack Pointer
Source Index
Destination Index
Register & Memory
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AX
BX
CX
DX
BP
SP
SI
DI
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Op Code
What To Do
Address
Location of Data
1101 101101100100
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The MAR & MDR are used for data exchange between
memory and the CPU.
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Zero Flag
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S 0 0 P 0 1 Z HC 1 1 0 C 1 0 V 1
PSW
Solution:
a) Represent the operands using 8-bit signed 2s complement
representation.
b) Perform the operation (Addition) and compute the result.
c) Find out the values of the binary Flags: S, Z, HC, C, P, V
d) Fill in the entries in the PSW Register.
e) Encode the Register contents using hexadecimal notation.
Register & Memory
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Decimal 2s Complements
12
11110100
16
11110000
11110100
+ 11110000
111100100
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00011011
1
00011100
Memory Organisation
Computer systems employ a memory
hierarchy.
At higher levels, memory is faster,
smaller & more expensive.
Within the CPU, there is a set of registers
that function at a level above main
memory & cache in the hierarchy.
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Slide 30 of 26
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Cache Memory
Generally speaking
The CPU asks for data/instructions from
memory faster than it receives from them.
This type of waiting is bad for performance
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Cache Memory
We can use these tendencies to advantage by keeping
likely to be referenced (soon) data in a faster memory
than main memory.
This faster memory is called a CACHE.
It is located very close to the processor.
It contains COPIES of PARTS of memory.
CPU
Main Memory
Cache
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Access drawer
in 5 s
Register
file
Access
desktop in 2 s
Cache
memory
Main
memory
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Memory Organisation
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Slide 35 of 26
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Memory Capacity
Memory Capacity is the maximum number
of addressable memory locations.
Let the size of the address be k bits and
the number of addressable memory
locations be M locations.
Then => M = 2k locations
If each location can accommodate B bytes,
then memory capacity in bytes is (2k * B).
Register & Memory
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Memory Capacity
2n x m
n - address bits = 2n addresses
m - data bits
m - the width of the data path
Typical values: n: 16, 17, 18, 19, 20, 21, 22, etc.
m: 8, 16, 32, 64
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Types of Memory
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Types of Memory
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Types of Memory
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Memory Slots
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DRAM
Faster
Slower
More complex
Simpler to build
No refresh
Needs refresh
More expensive
Less expensive
Cache
Main memory
Smaller
Larger
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Types of Memory
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Types Of Memory
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Slide 46 of 26
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Answers
Q1
512 = 29, K = 210, B = byte = 8bits = 23
29 x 210 x 23 = 222 = 4,194,304 bits
Q2
2 = 21, M = 220, B = byte = 8bits = 23
21 x 220 x 23 = 224 = 16,777,216 bits
Q3
MAR = 36bits
Total addressable locations = 236 = 68719476736 =
64GB
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Answers
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DX
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Q&A
Register & Memory
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