Design of an Error Detection and

Data Recovery Architecture for

Motion Estimation Testing
Applications
Presented by
S.Ratnakar
11AJ1D6813

Abstract:
The increased growth of sub-micron technology has
resulted in the difficulty of testing.
Based on those difficulties Motion estimation is also an
problem in video coding systems.
Generally Motion Estimation Computing Array can
performs upto 50% of computations.
Motion Estimation efficiency can be reduced by the
errors .

Motivation to the Work:

Video compression is necessary in in wide range of

applications.
Motion Estimation(ME) is of priority concern in exploiting

the temporal redundancy between the successive frames.

ME is the most computationally important part of video

coding.
ME consist Processing Elements.

Motivation to the Work:

To increase the performance of the Motion Estimation

we need to increase the reliability of the processing

elements.
To overcome the errors in the processing element it is

most important to introduce the design for testability.

Design for testability also focuses on reliability.

Literature Survey:
Design for testability can guaranteeing the circuit

reliability.
The DFT technique increase the ease of testing .
In olden days Built in self Diagnosis and Built in self

repair are used.

So totally error correction results complexity in the final

design.

Literature Survey:
In olden days we can use parity code, Berger code and

residue code.
Those codes can detect the errors only.
Residue code can detect only one error an it can not

be recovered effectively.
So, we need to introduce the new code.

Proposed Technique:
By observing the above drawbacks in existing

techniques we are proposing the Built in self test.

Built In Self Test(BIST) is one of the techniques in design

for testability.
We are proposing the residue quotient code(RQ code).
Finally we are proposing the Error Detection and Data

Recovery technique which utilizes BIST & RQ code.

Built In Self Test:

It can find the faults and their locations also.
Lower cost of test

Possibly shorter test times

Tests can be performed throughout the operational life of

the chip.

BIST Architecture:
Test Pattern Generation (TPG)

BIST
Control Unit

Circuitry Under Test

CUT

Test Response Analysis (TRA)

Detailed Architecture of BIST:

Proposed Technique:
This technique can detect the errors and recover the loosed

data.
It uses the BIST technique to locate and rectify the errors and

to recover the loosed data by using RQ code.

It comprises two major circuit designs,

Error Detection Circuit

Data Recovery Circuit

EDDR Architecture:
Primary
Inputs
CUT

TCG

EDC

DRC

S
E
L
E
C
T
O
R

Error free data

or data recovery
results

Advantages of Proposed architecture:

More reliability.
Less number of gate counts.

Tools Used:
VHDL

For the verification of circuit design

Synopsys Design Compiler

For the synthesis purpose of the proposed design

References:
Design of an Error Detection and Data Recovery Architecture for Motion Estimation
Testing Applications, 2012 IEEE .
Built-in self-detection/correction architecture for motion estimation computing
arrays, IEEE Transaction Very Large Scale Integrated (VLSI) Systems.,vol.55,Feb,
2010.
Testable design and BIST techniques for systolic motion estimators in the transform
domain, in Proc. IEEE International Conference Circuits Systems, Apr. 2009

Built-in self-test design of motion estimation computing array, in Proc. IEEE

Northeast Workshop Circuits Systems, Jun. 2004.

Thank You!!!