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i c c f m t
t t t c f m t dt c
S PM Ac cos c t c f m t dt
[1]
Vin
Corresponding DC bias
Cf
- Gain of VCO
Block Diagram
Input
DC Bias
Vcc/2
VCO
PA
Chipset
4046 Phase-Locked Loop
LM7171 Wide-Band Power Amplifier
741 Op Amp
4046 PLL
Schematic
PCB Layout
Measured Results
FM Receiver
i
s K pKv F s
1
f K v Ve
s
Ve
sK p F s
s Kv K pF s
s i C f m t
in
i
PFD
LF
VCO
Ve
n
R2C 0.7
2
K pKv
N R 1R2 C
[3]
VCO Design
VCO free running frequency = Carrier Frequency
VCO Frequency Range is no smaller than
Bandwidth
Large VCO gain will increase PLL natural frequency
n and thus improves PLL tracking capability
Block Diagram
BPF
LNA
PFD
LF
VCO
Amp
Chipset
4046 PLL
CLC425 Wide-band LNA
4046 PLL
Schematic
PCB Layout
Superheterodyne FM
Receiver
Block Diagram
Input
Matching
Mixer
IF Amp +
IF Filter
LO
FM
Demodulator
Amp
Chipset
TDA7000 FM Radio
LM3875 Audio Power Amplifier
TDA7000
[4]
IF Filter
Quadrature Demodulator
Hs
1
R2 1 j R1 R2 C
Vout
fin
IF Harmonic Distortion
RF 75kHz
IF=70kHz
2 IF IF IF IF IF 15kHz
IF Distortion Suppression
FLL
Correlator
To suppress interstation noise
Not Modulated
Lightly Modulated
Heavily Modulated
Schematic
PCB Layout
Block Diagram
PLL
Reference
Frequency
Dual Modulus
Prescaler
Digital
Input
Analog
Input
A/D
Converter
Shift
Register
Clock
Data
Sampling
Rate
Output
Inverter
NAND 2 Input
NAND 3 Input
NAND 4 Input
NOR 2 Input
XOR
Transmission Gate
Edge-Triggered D Flip-Flop
Voltage Comparator
8-to-3 Encoder
A/D Converter
Phase-Frequency Detector
VCO
[6]
Output Driver
To drive capacitive load with minimum delay
A 0 W n ,W p
A1 Wn ,W p
A N 1 Wn ,W p
N ln
CL
Cin
CL
Cin
1
N
Synthesizer
Synthesizer Response
Chip Layout
Noise Mechanism
Digital switching injects current into substrate through
various kinds of capacitance, which propagates through
the substrate and affects analog circuits.
Digital switching draws current from power supply rail
with impedance and thus creates voltage drop on power
supply rail.
PFD
LF
VCO
Noise Coupling
/N
Simulation Results
Error Voltage
VCO output
Test Structure 1
PFD
LF
VCO
/N
Chip Layout 1
Test Structure 2
PFD
LF
VCO
/N
Chip Layout 2
Test Structure 3
PFD
LF
VCO
/N
Guard Ring
p+
Sink the coupling
P-type Substrate
p+
On-Chip Shielding
Metal 3
Via2
Via1
Contact
Ohmic Contact
ICs
Radiation
Chip Layout 3
Test Structure 4
PFD
LF
VCO
/N
The counter uses separate power supply rails
Use guard rings around PFD and VCO
Implement LC VCO
LC VCO
Lower Phase Noise than Ring Oscillator
Oscillator Basics
Positive feedback of 2n phase shift
Unity loop gain
rp
- Tank Loss
0
gm
Q
[8]
1
LC
1
rp
rp
V1
g mV1
rp
0L
Chip Layout
Electromagnetic Coupling
L
W
1
S
2
[9]
Even Mode
Odd Mode
Impedance Matrix
cot l
2
cot l
j Z oe Z oo
2
csc l
j Z oe Z oo
2
csc l
j Z oe Z oo
2
j Z oe Z oo
cot l
2
cot l
j Z oe Z oo
2
csc l
j Z oe Z oo
2
csc l
j Z oe Z oo
2
j Z oe Z oo
csc l
2
csc l
j Z oe Z oo
2
cot l
j Z oe Zoo
2
cot l
j Z oe Z oo
2
j Z oe Zoo
2 c2
csc l
2
csc l
j Z oe Z oo
2
cot l
j Z oe Z oo
2
cot l
j Z oe Z oo
2
j Z oe Z oo
Different Configurations
Low Pass
Band Pass
Band Pass
Band Pass
Experiment Setup
f 100MHz 2.9GHz
P 0dBm
Signal
Generator
FR-4 Substrate
Ground Plane
Spectrum
Analyzer
f ?
P ?
Results
[10]
References
1.
2.
3.
4.
5.