Hardware Description

Language - VERILOG

What Will We Learn?

HDL-

based design flow

History of Verilog
Verilog design and module structure
Verilog representation models
Combinational and Sequential circuits
in Verilog
Recommended Verilog coding styles

HDL-based design flow

For

ASICs, verification and fitting

phases are usually much longer
(as a fraction of overall project
time) than design entry phase.

Verilog
Verilog

(sometimes called Verilog HDL) is a

hardware description language (HDL) used
to model electronic systems.
The language supports the design,
verification, and implementation of analog,
digital, and mixed-signal circuits at various
levels of abstraction.
Synthesis became practical in the early 90s and
use of Verilog and VHDL has taken off since
then
Only

a subset of the language can be

synthesized.
4

History of Verilog (1/2)

Beginning

Verilog was invented at Automated Integrated Design Systems

(later renamed to Gateway Design Automation) in 1985 as a
hardware modeling language. Gateway Design Automation was
later purchased by Cadence Design Systems in 1990.

Verilog-95

(IEEE Standard 1364-1995)

With the increasing success of VHDL at the time, Cadence

transferred Verilog into the public domain under the Open Verilog
International (OVI) (now known as Accellera) organization. Verilog
was later became IEEE Standard 1364-1995.

Verilog

2001 (IEEE Standard 1364-2001)

Extensions to Verilog-95 were submitted back to IEEE to cover the

deficiencies that users had found in the original Verilog standard.
Verilog-2001 is a significant upgrade from Verilog-95, including
support for signed nets and variables, more succinct built-in
operators, generate/endgenerate construct, improved file I/O, and
a few syntax additions to improve code-readability.
Verilog-2001 is the dominant flavor of Verilog supported by the
majority of commercial EDA software packages.
5

History of Verilog (2/2)

Verilog

2005 (IEEE Standard 1364-2005)

Verilog 2005, focus mostly on minor corrections.

The latest versions of the language include
support for analog and mixed signal modelling.
These are referred to as Verilog-AMS.

SystemVerilog

(IEEE standard P1800-2005)

Systemverilog is a superset of Verilog-2005,

with many new features and capabilities to aid
design-verification and design-modeling.
The advent of High Level Verification languages
encouraged the development of Superlog by CoDesign Automation Inc., which was later
purchased by Synopsys. The foundations of
Superlog and Vera were donated to Accellera,
which later became the SystemVerilog.
6

Verilog Module Concept

Text file: my_module.v

System

is a collection
of modules.
Everything you write
in Verilog must be
inside a module
Exception: compiler
directives
in1
in2

module my_module(in1, ..., outM);

input in1, ..., inN;
output out1, ..., outM;
... // declarations
... // description of f
... // (may be sequential)
endmodule

my_module

out1
out2

f
inN

outM
7

Hierarchical Design

A design may be described in a hierarchy of other

modules. The top-level module is the complete
design, and modules lower in the hierarchy are the
designs components.
Module instantiation is the construct used for
bringing a lower level module into a higher level one.

Verilog Module Definition

module Module_Name (port_name, ...);
{module_port_declarations}
{data_type_declarations}
{continuous_assignments}
{module_instances}
module
{primitive_instances}
items
{procedural_blocks}
{task_definitions}
{function_definitions}
{specify_blocks}
endmodule
Module

module mylogic (W, X, Y, Z);

input W, X;
output Y, Z;
reg Z;
assign Y = W & ~X;
always @ (W or X)
begin
Z=0;
if (!X) Z=W;
end
endmodule

functionality may be:

Structural - modeled as a netlist of module instances or primitive instances.

Behavioral - modeled with procedural blocks or continuous assignment
statements.
A combination of structural and behavioral.

Module

definitions may not be nested. Instead, modules

instantiate other modules.
Module items may appear in any order, but port declarations
and data type declarations should be listed before the ports or
signals are referenced.
9

Verilog Lexical
Conventions
Verilog

is:

Case sensitive
Based on the C programming language
White

space characters:

spaces, tabs, newlines (carriage return),

formfeeds and EOF (end-of-file).
List

separator: ,
Statement terminator: ;
Comments
//
[end of line]
/* Multiple line
comment
*/
/* Nesting /* comments */ DO NOT work */
10

Verilog Value Set

Verilog

has 4 logic values:

0 represents low logic level or false
condition
1 represents high logic level or true
condition
x or X represents unknown logic level
z or Z
represents high impedance
logic level
11

Verilog Number Notations

(1/2)

Constants

Format: <size>'<radix> <value>

No
Noof
of
bits
bits

Binary

Binary
bbor
orBB
Octal

Octal
ooor
orOO
Decimal

Decimal
ddor
orDD
Hexadecimal
Hexadecimal
hhor
orHH

Consecutive
Consecutivechars
chars
0-f,
0-f,x,x,zz

Binary

Single bit: 1'b0, 1'b1

Multiple bit:6'b110001, 6'B11_0001 (underline permitted
for readability)

Other bases

Octal 6'o61, 6'O6_1

Hex 8'h31, 8'H3_1
Decimal 49
Real 4.9E-1, 4.9e1

12

Verilog Number Notations

(2/2)
Bit

extension

MS bit = x or z

extend this

4b x1 = 4b xxx1

MS bit = 0 or 1

zero extension

4b 1x = 4b 001x

When

size is less than value, the upper bits are

truncated.
If size is omitted it
is inferred from the value or
takes the simulation specific number of bits or
takes the machine specific number of bits
If

radix is omitted too .. decimal is assumed

15 = <size>d 15
13

Verilog Identifiers
Identifiers

Must begin with alphabetic or underscore

characters: a-z A-Z _
May contain the characters: a-z A-Z 0-9 _ and
$
May use any character by escaping with a
backslash ( \ ) at the beginning of the
identifier, and terminating with a white space.
Examples:

myidentifier
m_y_identifier
3my_identifier
$my_identifier
_myidentifier$
\module*

Case sensitivity
myid Myid

14

Verilog Keywords
Keywords

Words reserved for special meanings

Cannot be used as identifiers, except when
using backslash
Examples: module, begin, and, if
To avoid mistakenly using keyword as
identifier, simply observe syntax coloring
in Verilog editor. Keywords are highlighted
in blue in Quartus II.

15

Verilog Module Port

Declarations
Verilog-1995

requires all module header ports to be

declared two or three times, depending on the
data type used for the port.
Z output has to be declared 3 times, once in the
module header port list, once in an output port
declaration and once in a reg (variable) data-type
declaration.
Verilog-2001 combines the header port list
declaration, port direction declaration and data-type
declaration into a single declaration
Verilog-1995

Verilog-2001

module mylogic (W, X, Y, Z);

input W, X;
output Y;
output [7:0] Z;
reg [7:0] Z;
...
endmodule

module mylogic (
input W, X,
output Y,
output reg [7:0] Z
);
...
endmodule

16

Verilog Data Type

Declarations

Nets/Signals

are declared as wire.

Wires are used for interconnections and have
properties of actual signals in a hardware
component.
Net declaration examples:
wire bit1, bit2;
// single-bit wires
wire [2:0] bus_wire;
// 2 is MSB and 0 is LSB
wire [0:7] big_endian; // 0 is MSB and 7 is LSB
Variables

are declared as reg. Note that reg

(register) is not necessarily hardware register.
Variables are used for behavioral descriptions and
are very much like variables in software languages.
Variable declaration examples:
reg [31:0] unsigned_var;
// Unsigned variable
reg signed [7:0] signed_var; // Verilog-2001 only

17

Verilog Representation
Models

Structural

Define explicit or primitive components and the

connections between them.
Textual equivalent of drawing a schematic.
Dataflow
Assign expressions to nets using continuous
assignments.
Uses various operators, including arithmetic,
relational, logical, bit-wise, reduction, concatenation,
replication operators.
Behavioral
Write an algorithm that describes the circuits output.
May not be synthesizable or may lead to a very large
circuit.
18

Design Abstraction & Design

Model
Abstraction Levels

Design Model

Algorithmic

FSM

Behavioral /
Data Flow

How it works

RTL

C
Gate

Structural

Layout

Physical

How it is
connected
How it is
implemented
19

FSM Abstraction Level

Finite State Machine

Controller part of a digital

design

E0
E1

ck, ...

Internal states
E2

State changes driven by:

E3

Status information
Clock and other external inputs...
20

RTL Abstraction Level

Register Transfer Level
Registers connected by
combinatorial logic
Very close to the hardware

DIN

DOUT
COMBINATIONAL
LOGIC

REGISTERS

CLOCK

21

Gate Abstraction Level

A gate net-list describing instantiation of models

CIN

A
B

SUM

COUT

22

Structural Model for 2-to-4 Decoder

(1/2)

module V2to4dec (
input I0, I1, EN,
output Y0, Y1, Y2, Y3
);
23

Structural Model for 2-to-4 decoder (2/2)

Built-in primitive
instances
not
not
and
and
and
and

U1
U2
U3
U4
U5
U6

(NOTI0, I0);
(NOTI1, I1);
(Y0, NOTI0, NOTI1,
(Y1,
I0, NOTI1,
(Y2, NOTI0,
I1,
(Y3,
I0,
I1,

Implicitly declare wires

for gate instantiation
outputs
EN);
EN);
EN);
EN);

endmodule

Instance names 1 output followed

by 1 or more inputs

24

Dataflow Model for 74x138 3-to-8

decoder
module V74x138 (
input G1, G2A_L, G2B_L, // enable inputs
input [2:0] A,
// select inputs
output [0:7] Y_L);
// decoded outputs
wire G2A, G2B;
wire [0:7] Y, Y_s;

// active-high version of inputs

// active-high version of signals

assign G2A = ~ G2A_L;

// invert
assign G2B = ~ G2B_L;
// invert
assign Y_L = ~ Y;
// invert
assign Y_s =
(A == 3'b000) ? 8'b10000000 :
(A == 3'b001) ? 8'b01000000 :
(A == 3'b010) ? 8'b00100000 :
(A == 3'b011) ? 8'b00010000 :
(A == 3'b100) ? 8'b00001000 :
(A == 3'b101) ? 8'b00000100 :
(A == 3'b110) ? 8'b00000010 :
(A == 3'b111) ? 8'b00000001 :
8'b00000000;
assign Y = (G1 & G2A & G2B) ? Y_s
endmodule

inputs
inputs
outputs

Note: All assignment

statements operate
concurrently
(combinational circuit).

: 8'b00000000;
25

Behavioral Model
Normally

uses Verilog procedural blocks

Each Verilog procedure executes in
parallel with other Verilog procedures and
continuous assignments
Continuous assignments include
assignment and select statements in
dataflow model
Concurrency is needed to model the
behavior of parallel, interconnected
hardware elements
But sequential statements can be used
within a procedure
26

Verilog Procedure
always @ (sensitivity list)
begin
local variable declarations
procedural statements
...
procedural statements
end

sequence of sequential
statements.
Activated when any signal
in the sensitivity list
changes.
Primarily a simulation
concept, but can be
synthesized
27

Procedural Statements
blocking/non-blocking

assignment

if-else
case
for

loop
while loop
repeat loop
infinite loop
disable
etc.
28

Behavioral Version of 74x138

module V74x138 (
input G1, G2A_L, G2B_L,
input [2:0] A,
output reg [0:7] Y_L);

// enable inputs
// select inputs
// decoded outputs

always @ (G1 or G2A_L or G2B_L or A)

begin
reg G2A, G2B;
// active-high version of inputs
reg [0:7] Y;
// active-high version of signals

Note that variable Y is

assigned twice,
exhibiting variable
behavior instead of
wire.

G2A = ~ G2A_L;
G2B = ~ G2B_L;
case (A)
3'b000:
3'b001:
3'b010:
3'b011:
3'b100:
3'b101:
3'b110:
3'b111:
endcase

Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=

// invert inputs
// invert inputs
8'b10000000;
8'b01000000;
8'b00100000;
8'b00010000;
8'b00001000;
8'b00000100;
8'b00000010;
8'b00000001;

if (G1 & G2A & G2B)

Y = Y;
else
Y = 8'b00000000;
Y_L = ~ Y;
end
endmodule

// invert outputs

29

Truly Behavioral Version

A wild card token @* is used to
represent a combinational logic
sensitivity list (supported in Verilog2001)

always @*
begin
integer i;
Y = 8'b00000000;
if (G1 & G2 & G3)
for (i=0; i<=7; i=i+1)
if (i==A) Y[i] = 1'b1;
end

May not be synthesizable, or may have a slow or

inefficient realization. But just fine for simulation
and verification.
30

Another Behavioral Example:

74x148 Priority Encoder
module V74x148 (
input EI_L,
input [7:0] I_L,
output reg [2:0] A_L,
output reg EO_L, GS_L
);
always @*
begin
reg EI;
// active-high version of
reg [7:0] I;
// active-high version of
reg EO, GS;
// active-high version of
reg [2:0] A;
// active-high version of
integer j;

input
inputs
outputs
outputs

EI = ~EI_L;
// invert input
I = ~I_L;
// invert inputs
EO = 1'b1; GS = 1'b0; A = 3'b000;
if (EI==1'b0)
EO = 1'b0;
else
begin : Loop
Observe the use of
for (j=7;j>=0;j=j-1)
if (I[j]) begin
disable statement
GS = 1'b1; EO = 1'b0; A = j;
disable Loop;
exit execution of a
end
end
named group (Loop)
EO_L = ~EO;
GS_L = ~GS;
A_L = ~A;
end
endmodule

to
of

statements
// invert output
// invert output
// invert outputs

31

Example
x
1
x
3

x
2
x
4

32

Structural Model
module

example2 (x1, x2, x3, x4, f, g, h);

input x1, x2, x3, x4;
output f, g, h;
and (z1, x1, x3);
and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);

endmodule
33

Behavioral Model
module

example4 (x1, x2, x3, x4, f, g,

h);
input x1, x2, x3, x4;
output f, g, h;

assign g = (x1 & x3) | (x2 & x4);

assign h = (x1 | ~x3) & (~x2 | x4);
assign f = g | h;

endmodule
34

Homework #1 : adder

Write the Verilog code for the 1-bit adder

using structural, behavioral and dataflow
representation model

35

Structural Model
module

Fulladder (A, B, Cin, S, Cout);

input A, B, Cin;
output S, Cout;
and (z1, A, B);
xor (z2, A, B);
xor (S, z2, Cin);
and (z3, z2, Cin);
or (Cout, z1,z3);

endmodule
36

Behavioral Model
module Fulladder (
input A,B,Cin
output S,Cout
);
assign {Cout,S} = A + B + Cin;
endmodule

37

Data Flow Model

module Fulladder (
input A,B,Cin
output S,Cout
);
wire z;
assign z = A^B;
assign S= z^Cin;
assign Cout = (a&b) | (z&Cin);
endmodule
38

Hierarchical Design

Verilog allows for a hierarchical model layout, which

means that a module can be assembled out of several
sub modules.
The connections between these sub modules are
defined within the architecture of a top module.
A purely structural architecture does not describe any
functionality and contains just a list of components,
their instantiation and the definition of their
interconnections.

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39

Module Instantiation
module FULLADDER (
input A, B, CARRY_IN,
output SUM, CARRY);

wire W_SUM, W_CARRY1, W_CARRY2;

HALFADDER module1 (A, B,
W_SUM, W_CARRY1);
HALFADDER module2 (W_SUM, CARRY_IN,
SUM, W_CARRY2);
or module3 (CARRY,
W_CARRY2, W_CARRY1);
endmodule
module HALFADDER (
input A, B,
output SUM, CARRY);
assign SUM = A ^ B;
assign CARRY = A & B;
endmodule
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(1/2)

A module is instanced
as a module item of
another module.
Signals are linked by
port order connection:
lists signal connections
in the same order as
the port list in the
module definition.
Unconnected ports are
designated by two
commas with no signal
listed.

40

Module Instantiation
A

(2/2)

module can be instanced as

often as necessary.
Each module instance is given a
unique label by the designer,
together with the name of the
module itself.
The choice of modules is
restricted to those that are
already defined some where else,
or the primitive modules.
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41

Module Instantiation:
Port Name Connection
module FULLADDER (
input A, B, CARRY_IN,
output SUM, CARRY);
wire W_SUM, W_CARRY1, W_CARRY2;

Port

name
connection:

HALFADDER module1 (.A(A), .SUM(W_SUM),

.B(B), .CARRY(W_CARRY1));

(.port_name(signa
l),
.port_name(signal
), ...);

HALFADDER module2 (.SUM(SUM),

.CARRY(W_CARRY2), .A(W_SUM),
.B(CARRY_IN));

Left side: port

names from submodule.
Right side: local
signal names (main
module)

or module3 (CARRY,
W_CARRY2, W_CARRY1);
endmodule
module HALFADDER (
...
endmodule

Port
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names can
be listed in any
order,
42

Port Assignments
module

reg or net

input

net

ports
module

reg or net

output

net

ports
module

net

inout

net

ports
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43

Primitive Instances
Gate Type

Terminal Order

Examples

and
or
xor

nand
nor
xnor

(1_output, 1-or-more_inputs)

and U1(X, A, B);

or U2(X, A, B, C);

buf

not

(1-or-more_outputs, 1_input)

not U3(X, A);

bufif0
bufif1

notif0
notif1

(1_output, 1_input,
1_control)

bufif0 U4(X, A, C);

user-definedprimitives

(1_output, 1-or-more_inputs)

C
A

Mux2_1 U6(X, A, B, S);

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44

Primitive Instances:
Half Adder Example
module HALFADDER (
input A, B,
output SUM, CARRY);
xor (SUM, A, B);
and (CARRY, A, B);
endmodule
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45

Quiz # 1
1) Write the Verilog code for a 1 bit
comparator using
a) Structural Model
b) Behavioral Model
2) Using the 1 bit comparator,
write a Verilog code for a 4 bit
comparator using both models as
above.

47