Investigation of High-Fidelity

Clock Generation and

Distribution for
Microprocessor Applications
Michael Lorek
Siva Thyagarajan
EE241 Spring 2010

Motivation
Accurate clocks (low jitter and 50% duty
cycle) are critical for high-speed digital
operation
Clock uncertainty causes relaxation of
operating frequency to meet timing constraints
NORA and A/D circuits sensitive to both clock
phases
50% duty cycle crucial

Background
Jitter is defined as time variation in
clock edges
Differential clock duty cycle is defined
as the percentage of the clock period
that the differential signal is greater
than zero

State-of-the-Art: Clock
Distribution
Intels latest Nehalem architecture employs a
modular design using multiple PLLs and clock
correction schemes
Adaptive Frequency System
Couples PLL VCO supply to digital supply so clock and
logic delays track together with supply droops

Duty Cycle Correction DCC systems

Analog and Digital circuits for different applications

State-of-the-Art: Jitter
Reduction
Second-order PLL equations:
1+ s
H(s) =
1+ s

2
N

2
1
+ s2
N
N 2

N RC1

N =

K PFD KVCO ICP

NC1

Self-biased
PLL jitter reduction

schemes make:

R ICP = Constant

Keeps optimal loop dynamics

constant vs. operating frequency
Digital jitter reduction techniques

measure
jitter and adjust loop to
compensate

State-of-the-Art: Duty Cycle

Correction
Intel Nehalem Digital
Implementation

Intel Nehalem
Analog
Implementation

PLL Circuit Design

3.2GHz 3rd order PLL Loop
with 2x locking range
200MHz reference input,
16X divide ratio

Began by choosing
=0.707, ICP = 20uA
Calculated R,C1,C2 using
equations given in slide 5

Current-starved
differential ring-oscillator
VCO

PLL Performance
VCO Control Voltage vs.
Time
Attains phase lock
around 400ns

PLL VCO Output Eye

Diagram
3.2GHz Clock

DCC Theory Analysis

Corrects for errors in duty cycle due to
mismatch in differential legs
Corrects DC shift through control loop that
creates current imbalance in output clock
generator

DC Bias equal, imbalanced duty

cycle

DC Bias mismatch, 50% duty

cycle

Intel Nehalem Analog DCC

DOUT

sCd Gcorr
=
Din
sCd + GcorrGdet

DCC Circuit Design

(t 0 )(mt 0 ) + (x)(mt 0 ) = (t1 )(mt1) + (y)(mt1 )

t 0 (t 0 + x) = t1 (t1 + y)
Required :2t 0 + x = 2t1 + y

Simulation Results I

Output duty cycle with DC offset of 60mV and 50%

clock duty cycle

Output duty cycle versus input duty

cycle

Output duty cycle with DC offset 41.6% clock duty c

Simulation Results II
Mismatched
VCO without
DCC Correction

Mismatched VCO
with DCC
Correction!

Conclusion and Further

Work
Worst case duty cycle output clock
variation of 2% with +/- 15% input duty
cycle
Mismatch-modeled PLL integrated with
DCC circuit results in 0.1% duty cycle error
at the output
Further work would involve extending the
possible range of duty cycle correction with
minimum error
Different technique likely required

May be possible to use DCC on a divide-bytwo version of the output to reduce longterm VCO clock jitter