Professional Documents
Culture Documents
(PIC18F14K50)
Autor:
PIC18 Arquitectura
Revisin
Slide 3
Familia PIC18
PIC18 Tradicional
PIC18 serie - J
PIC18 serie - K
4KB
32KB
128KB
Program Flash
Tipicamente los productos con mucha memoria tambien tienen muchos pines y perifericos avanzados integrados
Tradiciona PIC18
PIC18 serie J
PIC18 serie K
40 MHz, 10 MIPS, 5V
Flash endurance 100k
EEPROM
Caractersticas Premium
64MHz, 16 MIPS, 3V
Flash endurance 10k
EEPROM
Menor costo <32KB Flash
Slide 4
Espacio de
Datos
Tabla de
Acceso
8-bit
Memoria
Flash
Bus de
instrucciones
16-bit
8-bit
Bus de datos
8-bit CPU
8-bit
RAM
Peripfericos
Puertos I/O
Slide 5
ACCESS RAM
PIC18F2520/4520
Mapa de Registros
Banco0 GPR
Banco1 GPR
Banco2 GPR
ACCESS RAM
ACCESS SFR
Banco13 GPR
Banco14 GPR
Banco15 GPR
ACCESS SFR
Slide 6
Vector de Reset
000000h
000008h
000018h
Memoria de Programa
En el chip
007FFEh
008000h
Nivel de Stack 1
Nivel de Stack 2
Nivel de Stack 30
Nivel de Stack 31
Memoria de Programa
Sin implementar
(Read as 0)
Stack de 31 niveles
1FFFFEh
Slide 7
Tabla de Lectura
Arquitectura PIC 8-bit
TBLPTRU
TBLPTRH
TBLPTRL
00
00
09
0x000
22-bit Address
0x001
0x002
0x003
0x004
0x005
0x000001
0x000000
0x000003
0x000002
0x000005
0x000004
0x000007
0x000006
0x000009
TABLAT
2C
2C
0x000008
0x00000B
0x00000A
8-bit Data
0xFFA
0x1FFFF5
0x1FFFF4
0xFFB
0x1FFFF7
0x1FFFF6
0xFFC
0x1FFFF9
0x1FFFF8
0xFFD
0x1FFFFB
0x1FFFFA
0xFFE
0x1FFFFD
0x1FFFFC
0xFFF
0x1FFFFF
0x1FFFFE
Byte Alto
Byte Bajo
Slide 8
Caractersticas especiales
Como setear los bits de configuracin del PIC
Osciladores
Secundaria
Oscilador Timer1 Frecuencia fija
Necesario para base de tiempo de RTR
Oscilador Interno RC
INTOSC (8 MHz por default)
4, 2, 1 MHz, 500, 250, 125 y 31 kHz seleccionables
Slide 11
Slide 12
Slide 13
PIC18F
Caractersticas Especiales
Pin
Pin
VPP
PP
VDD
DD
VSS
SS
RB6
RB7
Function
Function
Programming Voltage
Supply Voltage
Ground
Clock Input
Data I/O & Command Input
ICSP Connector
Slide 15
Slide 16
Watchdog Timer
Ayuda al software a recuperarse de un mal
funcionamiento
Usa un oscilador libre RC en el chip
WDT es borrado por la instruccin CLRWDT
WDT Habilitable (WDTEN) no puede ser borrado por soft
el overflow (desborde) del WDT reetea al chip
Perodo del timeout programable : 18ms a 3.0s tpico
Opera en modo SLEEP; sobre el time out, despierta la
CPU.
Slide 17
VDD
MCLR
Circuito
RESET
en CHIP
Reset
Interno
VDD
MCLR
POR
PWRT
TPWRT
TOST
OST
Reset
Operacin
Slide 18
Slide 19
Slide 20
Slide 21
VREF interno
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 22
PIC18 RESETS
Power-on Reset (POR)
MCLR Reset durante la operacin normal
Programmable Brown-out Reset (BOR)
Watchdog Timer (WDT) Reset (durante la
ejecucin )
Instruccin RESET
Reset por Stack Full
Reset por Stack Underflow
Slide 23
STKPTR Register
STKFUL = 1: Stack over flow RESET
STKUNF = 1: Stack under flow RESET
Slide 24
Registro CONFIGlocalizado en la
memoria de programa, fuera del
area de ejecucin del cdigo
(inicia en @ 0x300000)
Reset Vector
High Interrupt Vector
Low Interrupt Vector
User
Memory
User Flash
Registros de Configuracin
Device ID
Configuration
Memory
Slide 26
Bits de Configuracin
PIC18F4520 (4 of 11)
CONFIG1H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IESO
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
CONFIG2L Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BORV1
BORV0
BOREN1
BOREN0
PWRTEN
bit 7
bit 0
CONFIG2H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
CONFIG3H Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MCLRE
LPT1OSC
PBADEN
CCP2MX
bit 7
bit 0
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 27
#fuses HS,NOWDT
options puede variar segun el
dispositivo. Un listado de las opciones
vlidas esta en el tope de cada archivo de
cabecera de cada dispositivo.
Slide 28
PIC18F1x50
Slide 29
Slide 30
USB Fundamentos
Un poco de historia...
USB fue co-desarrollado por un grupo de
compaas.
Compaq
Intel
Microsoft
NEC
quera hacer mucho mas facil el adicionar/remover
perifericos de la PCs
Slide 32
USB Basico
USB un maestro Single Master + Multiple Slaves bus encuestado
constantemente
USB Host Controller (Master)
y Root Hub
Mouse
Start Of Frame
Frame
Printer
Mouse Packets
Speakers Packets
Frame
2011 Microchip Technology Incorporated. All Rights Reserved.
Speakers
Printer Packets
Frame
Slide 33
Comparacin de Buses
1394-Fire Wire
Ethernet
WiFi (b/g)
USB 2.0
LS-USB
1.5 Mb/s
CAN
HS-USB
480 Mb/s
USB 1.1
Serial Port
500 Kb/s
FS-USB
12 Mb/s
Parallel Port
1 Mb/s
1.5 Mb/s
12 Mb/s
Slide 34
Grandes Mitos
Mito: un Perifrico USB Low-Speed puede transferir datos
hasta la velocidad de 187.5 KB/s (1.5 Mbps)
Slide 35
Real: Imposible, 1.5 MB/s es el total del ancho de banda del BUS
El ancho de banda se reparte entre todos los perifricos USB
El Over head del Protocolo
Las restricciones del Protocolo
La realidad de la transferencia de datos de un nico perifrico
puede llegar a ~1.0 MB/s en el mejor de los casos
Solo 64 KB/s en la mayora de los casos
Slide 36
Host (Tier 1)
Tier 2
Speaker
Hub
Tier 3
Logic
Analyzer
Hub
Tier 4
Printer
Hub
Tier 5
Tier 6
Tier 7
Keyboard
Hub
Hub
Data Logger
Hub
Slide 37
Interfaz Fsica
VBUS
VBUS
D+
D+
D-
D-
GND
GND
~ 5.0 V
~ 3.3 V
Debe usar
alimentacin externa
si se necesita mas de
uno
Slide 38
Conectores Standard
- USB 2.0 A
USB Host
B
FS, HS
Device
mini-B
FS, HS
Device
Slide 39
Conectores Standard
- Micro-USB -
Plugs y Receptaculos
Micro-B plug y receptaculo
Permitido en productos OTG y on OTG
Micro-A/B receptaculo
Permitido en productos OTG
Micro-A plug
Indicacual es escencialmente el host (OTG)
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 40
RAM
Endpoint 1 IN
LED
Caps-Lock
RAM
Endpoint 1 OUT
Slide 41
Data Glove
Ethernet
Adapter
Mouse
External
Hard Drive
PICkit 3
Starter Kit
Joystick
Keyboard
Modem
Communication Device
Class (CDC)
MPLAB
REAL ICE
in-circuit emulator
Custom Class
(Vendor Class)
Slide 42
El Proceso de Enumeracin
Power
(self/bus)
POWERED
Bus
reset
ATTACHED
DEFAULT
Cable
Connecte
d
Get Device
Descriptor
SUSPENDED
DETACHED
ADDRESS
Get
Descriptor
s
CONFIGURED
Slide 43
Auto-Deteccin: Full-Speed
Peripheral Device
VUSB 3.3 V
1.5 k5%
+5V
D+
Transceiver
DGND
USB
Connector
Slide 44
Auto-Deteccin: Low-Speed
Peripheral Device
VUSB 3.3 V
1.5 k5%
+5V
D+
Transceiver
DGND
USB
Connector
Slide 45
VUSB 3.3 V
resistores pull-up
dentro del chip!
+5V
D+
Transceiver
DGND
USB
Connector
Slide 46
Planeando la Alimentacin
- Arquitectura -
Function Controller +
Function
Slide 47
Planeando la Alimentacin
- Arquitectura -
High Power
100-500 mA desde el bus
Debe ser enumerado a low power (100 mA)
Device pide el bMaxPower
Host habilita la configuracin deseada
solicitando el Set_Configuration
Slide 48
Planeando la Alimentacin
- Arquitectura -
Slide 49
Planeando la Alimentacin
- Necesito Autoalimentacin? -
Slide 50
Planeando la Alimentacin
VDD
Power from
USB Cable
10F
Slide 51
VDD
I/O
Slide 52
Scalable USB
PIC MCU Portfolio
~50 USB PIC MCUs
Performance
PIC32
High Performance, Pin Compatible to PIC24F
80 MHz, 1.53 DMIPS/MHz
Up to 80 MIPS
64- & 100-Pin Packages
Up to 512 KB Flash
Up to 32 KB RAM
USB 2.0 Device, Embedded Host, OTG
PIC24F
Mid-Range, Capacitive-Touch Capable
Up to 16 MIPS
64-, 80- & 100-Pin Packages
Up to 256 KB Flash
Up to 16KB RAM
USB 2.0 Device, Embedded Host, OTG
PIC18F
Small, Low Power, Low Cost
Up to 12 MIPS
18- to 80-Pin Packages
Up to 128KB Flash
Up to 4KB RAM
USB 2.0 Device Support
a
gr
e
t
In
nm
o
r
B vi
LA En
P
M e nt
d
e
ifi lopm
n
U ve
De
d
te
t
en
32-bit
16-bit
8-bit
Migration
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 53
Slide 54
PICPerifricos Comunes
Slide 56
Puertos I/O
Puertos I/O
Hasta 70 pines bidireccionales
Los mismos estan multiplexados con Perifricos
Slide 58
Slide 59
Slide 60
Escribe
PORTx
o LATx
LATx
Lee
LATx
0 1 0 1 0 0 1 1
PORTx
(I/O Pins)
TRISx
Lee
PORTx
Direccin de Datos
0 0 1 1 0 1 0 0 (1 = IN, 0 = OUT)
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 61
PORTB Opciones
Todos lod pines del PORTB tienen resistores de PULL UP.
Un bit controla el pull up de todos los pines
INTCON2 Register
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
bit 7
bit 7
U-0
R/W-1
bit 0
bit 0
Slide 62
Slide 63
Conversor A/D:
A/D de 10-bit
CHS3:CHS0
In ADCON0 Register
AN12
AN12
AN9
AN8
AN7*
AN6*
AN5*
AN4
VREF+ / AN3
VREF- / AN2
AN10
VAIN
ADC
VREF+
AN1
ADRESH
ADRESL
VREF-
VDD
AN0
x0
x1
1x
0x
VSS
VREF Select VCFG1:VCFG0 In ADCON1 Register
2011 Microchip Technology Incorporated. All Rights Reserved.
ADC 10-bit
Escalando resultados
FS = Fondo de
escala
N-bits, 2N Codigos
posibles
Slide 66
ADC 10-bit
Escalando resultados
Ejemplo:
10-bits ADC => 210 = 1024 codigos
Escala de valores completa 0 5.12 V
Cual es el tamao de un bit?
Respuesta:
Tamao del Bit = 5.12 / 1024 = 5 mV
Slide 67
Slide 68
Adquisicin de la seal
Acquisition Time
Conversion Time
time
VC
ADRES
10
Tiempo de adquisicin
determinado por la
capacidad CHold y la
Impedancia de fuente
ADC
+
VC
-
CHOLD
VIN
time
SOURCE
RS < 10k
VSS
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 69
ADC Conversion
Acquisition Time
Conversion Time
Time
Acquisition
time
VC
ADRES
VIN
ADC Result
time
11 ADC Conversion
Clock cycles (TAD)
10
ADC
time
+
VC
-
CHOLD
VSS
Slide 70
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 7
bit 5-2
bit 0
CHS3:CHS0
Analog Channel Select Bits
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
1100 =
Channel 0 (AN0)
Channel 1 (AN1)
Channel 2 (AN2)
Channel 3 (AN3)
Channel 4 (AN4)
Channel 5 (AN5)
Channel 6 (AN6)
Channel 7 (AN7)
Channel 8 (AN8)
Channel 9 (AN9)
Channel 10 (AN10)
Channel 11 (AN11)
Channel 12 (AN12)
bit 1
bit 0
Slide 71
U-0
R/W-0
R/W-0
R/W-0*
R/W*
bit 7
R/W*
R/W*
bit 0
bit 5
bit 4
Slide 72
U-0
R/W-0
R/W-0
R/W-0*
R/W*
bit 7
R/W*
R/W*
bit 0
A = Analog Input
D = Digital I/O
Slide 73
U-0
R/W-0
R/W-0
R/W-0*
R/W*
R/W*
bit 7
R/W*
bit 0
NOTE: This parameter determines the value of TAD: the conversion time per bit.
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Selection bits
111 = FRC (Clock derived from A/D RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (Clock derived from A/D RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 74
Operation
ADCS2:ADCS0
PIC18F4520
2 TOSC
OSC
000
2.86 MHz
4 TOSC
OSC
100
5.71 MHz
8 TOSC
OSC
001
11.43 MHz
16 TOSC
OSC
101
22.86 MHz
32 TOSC
OSC
010
40.0 MHz
64 TOSC
OSC
110
40.0 MHz
RC
x11
At FOSC = 4 MHz:
TOSC = 1/FOSC
= .25 s
TAD
= 4TOSC
= 1 s
Slide 75
Slide 76
TAMP = 0.2 s
Slide 77
= 25pF
= 1k
= 2k
= 2.5k MAX
Slide 78
Slide 79
Slide 80
U-0
R/W-0
R/W-0
R/W-0*
R/W*
R/W*
bit 7
R/W*
bit 0
Given:
TACQ = 2.4 s
TAD = 1 us
Then:
ACQT2:0 = 010 = 4.0 s
000 = 0 TAD
Slide 81
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 7
R/W-0
bit 0
bit 7
ADRESL
b99
b88
b77
b66
b55
b44
b33
b22
b11
b00
0 = Justificado a la izquierda
ADRESH
b99
b88
b77
ADRESL
b66
b55
b44
b33
b22
b11
b00
Slide 82
Slide 83
Timers
Timer Comparativa
TIMER 0
TIMERS 1 & 3
TIMERS 2 & 4
SIZE OF REGISTER
8-bits or
16-bits
16-bits
8-bits
CLOCK SOURCE
(Internal)
Fosc/4
Fosc/4
Fosc/4
CLOCK SOURCE
(External )
T0CKI pin
T13CKI pin or
Timer 1 oscillator
(T1OSC)
None
CLOCK SCALING
AVAILABLE
(Resolution)
Prescaler 8-bits
(1:21:256)
Prescaler 2-bits
(1:1, 1:2, 1:4, 1:8)
Prescaler
(1:1,1:4,1:16)
Postscaler
(1:11:16)
INTERRUPT EVENT
On overflow
FFh00h
On overflow
FFFFh0000h
NO
YES
NO
Slide 85
Timer0
Modo compatible con PIC16
8-bit Timer/Counter
Prescaler Programable de 8 bits
Fuente de clock externa o interna
Interrupcin sobre el overflow de FF a 00
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
TMR0L
T0CS
T0PS2:T0PS0
PSA
8-bit Data Bus
Slide 86
Timer0
Modo 16-bit
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
T0CS
T0PS2:T0PS0
Clock
Sync
High Byte
TMR0L
READ
TMR0L
PSA
WRITE
TMR0L
TMR0H
Slide 87
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
T0CS
T0PS2:T0PS0
PSA
DATA BUS
T0CON Register
TMR0ON
T08BIT
TMR0L
T0CS
T0SE
PSA
T0PS2:0
T08BIT
1 = 8 BIT
0 = 16 BIT
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 88
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
READ
TMR0L
T0CS
T0PS2:T0PS0
PSA
T0CON Register
TMR0ON
T08BIT
T0CS
High Byte
TMR0L
WRITE
TMR0L
TMR0H
DATA BUS
T0SE
PSA
T0PS2:0
T08BIT
1 = 8 BIT
0 = 16 BIT
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 89
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
READ
TMR0L
T0CS
T0PS2:T0PS0
High Byte
PSA
TMR0L
WRITE
TMR0L
TMR0H
T0CON Register
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2:0
Slide 90
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
TMR0L
READ
TMR0L
T0CS
T0PS2:T0PS0
High Byte
PSA
WRITE
TMR0L
TMR0H
T0CON Register
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2:0
Slide 91
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
READ
TMR0L
T0CS
T0PS2:T0PS0
High Byte
PSA
TMR0L
WRITE
TMR0L
TMR0H
T0CON Register
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2:0
Prescaler Assignment
1= prescaler NOT assigned
0= prescaler IS assigned
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 92
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
TMR0L
READ
TMR0L
T0CS
T0PS2:T0PS0
High Byte
PSA
WRITE
TMR0L
TMR0H
PS2
PS1
PS0
TMR0
RATE
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
DATA BUS
T0CON Register
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2:0
Slide 93
Timer0 Operation
FOSC/4
TMR0IF
0
1
T0CKI
T0SE
Programmable
Prescaler
Clock
Sync
READ
TMR0L
T0CS
T0PS2:T0PS0
High Byte
PSA
TMR0L
WRITE
TMR0L
TMR0H
T0CON Register
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2:0
TMR0ON
1 = ON
0 = STOPPED
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 94
Slide 95
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
RD16
Bit 7
T1RUN
TCKPS1:0 T1OSCE
N
T1CON Register
WRITE
TMR1L
TMR1H
Bit 0
Slide 96
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
TMR1ON
TMR1IF
TMR1H
T1RUN
TCKPS1:0
TMR1L
Clear Timer 1
(CCP Special Event Trigger)
T1CON Register
RD16
T1SYNC
TMR1CS
T1CKPS1: T1CKPS0
T1OSCEN
T1SYNC
TMR1CS TMR1ON
Bit 7
Bit 0
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 97
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
WRITE
TMR1L
TMR1H
T1CON Register
RD16
T1RUN
TCKPS1:0
Bit 7
Bit 0
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 98
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
WRITE
TMR1L
TMR1H
T1CON Register
8-bit Data Bus
RD16
T1RUN
TCKPS1:0
T1OSCEN
T1SYNC
TMR1CS TMR1ON
Bit 7
Bit 0
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 99
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
Bit 7
TCKPS1:0
High Byte
TMR1L
READ
TMR1L
T1CON Register
T1RUN
TMR1ON
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
RD16
T1SYNC
TMR1CS
T1CKPS1: T1CKPS0
T1OSCEN
WRITE
TMR1L
TMR1H
Bit 0
Slide 100
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
T1CON Register
RD16
Bit 7
T1RUN TCKPS1:0
WRITE
TMR1L
TMR1H
T1OSCEN
Slide 101
T1OSO/
T13CKI
FOSC/4
T1OSI
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
TMR1IF
High Byte
TMR1L
READ
TMR1L
T1CON Register
Bit 7
TMR1ON
T1CKPS1: T1CKPS0
Clear Timer 1
(CCP Special Event Trigger)
T1RUN
T1SYNC
TMR1CS
RD16
TCKPS1:0 T1OSCEN
WRITE
TMR1L
TMR1H
Slide 102
T1OSO/
T13CKI
FOSC/4
T1OSI
T1CON Register
Bit 7
T1RUN
Sync
Detect
TCKPS1:0 T1OSCEN
Sleep Input
T1OSCEN
RD16
Prescaler
1, 2, 4, 8
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
WRITE
TMR1L
TMR1H
Bit 0
Slide 103
T1OSO/
T13CKI
T1OSI
FOSC/4
Prescaler
1, 2, 4, 8
Sync
Detect
Sleep Input
T1OSCEN
Timer On
1 = Enables Timer
0 = Stops Timer
T1SYNC
TMR1CS
TMR1ON
T1CKPS1: T1CKPS0
TMR1IF
Clear Timer 1
(CCP Special Event Trigger)
High Byte
TMR1L
READ
TMR1L
T1CON
Register
RD16
TCKPS1:0
T1RUN
Bit 7
T1OSCEN
WRITE
TMR1L
TMR1H
Bit 0
Slide 104
Timer2
8-bit Timer with prescaler and postscaler
Used as PWM time base
TMR2 is readable & writable
TMR2 resets on match with PR2
Match with PR2 generates interrupt
Used as baud clock for MSSP (SPI )
Slide 105
Timer2
T2CON Register
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 0
bit 7
00 = 1:1
01 = 1:4
1x = 1:16
0000 = 1:1
0001 = 1:2
1:1 to 1:16
Postscaler
1111 = 1:16
TMR2IF
T2CKPS1:T2CKPS0
Reset
FOSC/4
TMR2
Timer 2 Output
(To PWM or MSSP)
TMR2/PR2 Match
Comparator
PR2
Slide 106
Slide 107
PIC18 Interrupts
Interrupcin
Definicin
Slide 109
Lgica de Interrupcin
Modo Legal o compatible con PIC16
TMR0IF
Core Interrupts
TMR0IE
Other Core
Interrupts
TMR1IF
TMR1IE
Wakeup
to CPU
Peripheral
Interrupts
Interrupt
to CPU
Vector to 0x0008
Other
Peripheral
Interrupts
GIE
PEIE
Slide 110
Lgica de Interrupcin
Modo Prioridad
IP
IE
IF
INT0IF
INT0IE
GIEH
Vector to 0x0008
High Priority
Interrupt to CPU
Wakeup to CPU
IP
IE
IF
Low Priority
Interrupt to CPU
GIEL
Vector to 0x0018
Slide 111
Slide 112
IPEN
SBOREN
---
RI
TO
PD
POR
BOR
Slide 113
PSPIP
PSPIP:
ADIP:
RCIP:
TXIP:
ADIP
RCIP
TXIP
SSPIP
SSPIP:
CCPIP:
TMR2IP:
TMR1IP:
CCP1IP
TMR2IP
TMR1IP
IPR2 Register
OSCIP
CMIP
---
EEIP
BCLIP
BCLIP:
HLVDIP:
TMR3IP:
CCP2IP:
HLVDIP
TMR3IP
CCP2IP
Slide 114
PSPIF
PSPIF:
ADIF:
RCIF:
TXIF:
ADIF
RCIF
TXIF
SSPIF
SSPIF:
CCPIF:
TMR2IF:
TMR1IF:
CCPIF
TMR2IF
TMR1IF
PIR2 Register
OSCIF
CMIF
---
EEIF
BCLIF
BCLIF:
HLVDIF:
TMR3IF:
CCP2IF:
HLVDIF
TMR3IF
CCP2IF
Slide 115
PSPIE
PSPIE:
ADIE:
RCIE:
TXIE:
ADIE
RCIE
TXIE
SSPIE
SSPIE:
CCPIE:
TMR2IE:
TMR1IE:
CCPIE
TMR2IE
TMR1IE
PIE2 Register
OSCIE
CMIE
---
EEIE
BCLIE
BCLIE:
HLVDIE:
TMR3IE:
CCP2IE:
HLVDIE
TMR3IE
CCP2IE
Slide 116
RBPU
---
TMR0IP
---
RBIP
INT2IP
INT2IP:
INT1IP:
INT1IP
---
INT2IE
INT1IE
---
INT2IF
INT1IF
Slide 117
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
---
INT2IF
INT1IF
INT2IP
INT1IP
--INT2IF:
INT1IF:
INT2IE
INT1IE
Slide 118
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INT2IF
INT1IF
INT2IP
INT1IP
--INT2IE:
INT1IE:
INT2IE
INT1IE
---
Slide 119
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PEIE/GIEL :
Peripheral Interrupt Enable (PIC16 Compatibility Mode) /
Global Interrupt Enable Low (Priority Mode)
In PIC16 Compatibility Mode (RCON<IPEN> = 0):
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
In Priority Mode (RCON<IPEN> = 1):
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 120
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
GIE/GIEH :
Global Interrupt Enable (PIC16 Compatibility Mode) /
Global Interrupt Enable High (Priority Mode)
In PIC16 Compatibility Mode (RCON<IPEN> = 0):
1 = Enables all unmasked interrupts
0 = Disables all interrupts
In Priority Mode (RCON<IPEN> = 1):
1 = Enables all high priority interrupts
0 = Disables all high priority interrupts
2011 Microchip Technology Incorporated. All Rights Reserved.
Slide 121
Slide 122
Thank You!
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear
Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB,
PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart
Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
Slide 124