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finite state vending machine for ME Applied ELectronics

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Outline

Review of sequential machine design

Moore/Mealy Machines

FSM Word Problems

Finite string recognizer

Traffic light controller

Computer Hardware = Datapath + Control

Registers

Combinational Functional

Units (e.g., ALU)

Busses

Qualifiers

Control

Control

of control signals

Instructs datapath what to

do next

strings"

State

Control

Signal

Outputs

Qualifiers

and

Inputs

"Puppet"

Datapath

3

Assert output whenever input bit stream has odd # of 1's

Reset

0

Even

[0]

1

1

Odd

[1]

State

Diagram

Present State

Even

Even

Odd

Odd

Input

0

1

0

1

Next State

Even

Odd

Odd

Even

Output

0

0

1

1

Present State

0

0

1

1

Input

0

1

0

1

0

0

1

0

1

1

0

1

4

Next State/Output Functions

NS = PS xor PI; OUT = PS

Input

NS

Input

CLK

R

CLK

PS/Output

\Reset

T FF Implementation

D FF Implementation

1

Output

Q

R

\Reset

Input

Clk

Output

ECE C03

Lecture

Timing Behavior:

Input

1 0120 1 1 0 1 0 1 1 1 0

1

5

When are inputs sampled, next state computed, outputs asserted?

State Time: Time between clocking events

Clocking event causes state/outputs to transition, based on inputs

For set-up/hold time considerations:

Inputs should be stable before clocking event

After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately

Synchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediately

sync. counter clear: effective at next clock event

6

Example: Positive Edge Triggered Synchronous System

State Time

Clock

outputs, next state computed

After propagation delay, outputs and

next state are stable

Inputs

Immediate Outputs:

affect datapath immediately

could cause inputs from datapath to change

Outputs

Delayed Outputs:

take effect on next clock edge

propagation delays must exceed hold times

1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state mininimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;

4, 5 generalized from the counter design procedure

General Machine Concept:

deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Step 1. Understand the problem:

Draw a picture!

Block Diagram

N

Coin

Sensor

D

Reset

Vending

Machine

FSM

Open

Gum

Release

Mechanism

Clk

Step 2. Map into more suitable abstract representation

Reset

three nickels

nickel, dime

dime, nickel

two dimes

two nickels, dime

Draw state diagram:

N

S1

Inputs: N, D, reset

Output: open

D

S2

S4

S5

S6

[open]

[open]

[open]

S3

S0

S7

S8

[open]

[open]

10

Step 3: State Minimization

Present

State

Reset

0

0

N

5

D

N

10

D

10

N, D

15

[open]

15

reuse states

whenever

possible

Inputs

D N

0

0

1

1

0

0

1

1

0

0

1

1

X

0

1

0

1

0

1

0

1

0

1

0

1

X

Next

State

Output

Open

0

5

10

X

5

10

15

X

10

15

15

X

15

0

0

0

X

0

0

0

X

0

0

0

X

1

11

Step 4: State Encoding

Present State Inputs

Q1 Q0

D N

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Next State

D1 D0

Output

Open

0 0

0 1

1 0

X X

0 1

1 0

1 1

X X

1 0

1 1

1 1

X X

1 1

1 1

1 1

X X

0

0

0

X

0

0

0

X

0

0

0

X

1

1

1

X

12

Step 5. Choose FFs for implementation

Q1

Q1 Q0

DN

0

Q1 Q0

DN

N

D

Q0

K-map for D1

Q1

D

Q0

N

N

\ Q0

Q0

\N

Q1

N

Q1

D

D1

D FF easiest to use

Q1

1

N

D

Q0

K-map for D0

D

CLK

Q1

\ Q1

Q1

Q1 Q0

DN

0

Q0

K-map for Open

D1 = Q1 + D + Q0 N

\reset

OPEN

D0

CLK

\reset

Q0

\ Q0

D0 = N Q0 + Q0 N + Q1 N + Q1 D

OPEN = Q1 Q0

8 Gates

13

Representations

Not flexible enough for describing very complex finite state machines

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algorithm: that is, well specified

sequence of actions based on input data

algorithm = sequencing + data manipulation

separation of control and data

Algorithmic State Machine (ASM) Notation

Hardware Description Languages (e.g., VHDL)

14

Representations

Algorithmic State Machine (ASM) Notation

Three Primitive Elements:

State Box

Decision Box

Output Box

State Machine in one state

block per state time

Single Entry Point

Unambiguous Exit Path

for each combination

of inputs

Outputs asserted high (.H)

or low (.L); Immediate (I)

or delayed til next clock

State

Entry Path

State Code

*

State

Name

State

Output List

T

***

State Box

Condition

Condition

Box

Conditional

Output List

ASM

Block

Output

Box

Exits to

other ASM Blocks

15

ASM Notation

Condition Boxes:

Ordering has no effect on final outcome

Equivalent ASM charts:

A exits to B on (I0 I1) else exit to C

A

010

I0

T

010

I1

T

F

I1

F

F

I0

T

B

C

16

Input X, Output Z

Even

Z asserted in State Odd

F

X

T

Odd

1

H.Z

Trace

Tracepaths

pathsto

toderive

derive

state

transition

state transitiontables

tables

Present Next

Input State

State Output

F

Even

Even

T

Even

Odd

F

A

Odd

Odd

T

A

Odd

Even

Encoded State Table:

Present Next

Input State

State Output

0

0

0

0

1

0

0

1

0

1

1

1

1

1

1

0

17

0

00

10

10

F

F

F

F

15

01

11

H.Open

T

N

F

F

Reset

T

T

0

18

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