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Description Language
system
VHDL standard
VHDL
Verilog
Complex grammar
Easy language
No user-defined packages
Library
Entity
list of libraries
Architecture
VHDL code
Netlist
optimization
Physical device
simulation
Library
Entity
list of libraries
Architecture
VHDL code
Syntax
LIBRARY library_name;
USE
library_name.package_name.package_par
Three t;different libraries
ieee
standard
work
ieee.std_logic_1164
standard
work
std_logic_1164
std_logic
std_ulogic
std_logic_arith
(8 levels)
(9 levels)
Comparison operators
Syntax
ENTITY
entity_name IS
PORT (
Port_name: signal_mode
signal_type;
Port_name: signal_mode
signal_type;
.)
entity_name;
Signal END
mode:
IN, OUT, INOUT, BUFFER
Syntax
ARCHITECTURE architecture_name OF
entity_name IS
[declaration]
BEGIN
(code)
END architecture_name;
Two parts:
Code part
types
subprograms
components
signal declarations
Case insensitive
Comments
--
If you want to comment multiple lines, -- need to be put at the
beginning of every single line
<=
18
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
PORT (A,B,C,D : IN STD_LOGIC;
E
: OUT STD_LOGIC);
END TEST;
ARCHITECTURE BEHAVIOR OF TEST IS
SIGNAL X,Y : STD_LOGIC;
BEGIN
X <= A AND B;
Y <= C AND D;
E <= X OR Y;
END BEHAVIOR;
Dataflow modeling
Behavioral modeling
Structural modeling
Dataflow modeling
Behavioral modeling
Process statements
Sequential statements
Signal assignment statements
Wait statements
It contains
sequential statements
variable assignment (:=) statements
signal assignment (<=) statements
Anatomy of a Process
OPTIONAL
Sensitivity List
process (sensitivity
list)
declaration part
begin
statement part
Every time the process fires, it will
run in its entirety
end process;
Declaration Part
process (sensitivity
list)
declaration part
begin
statement part
end process;
Statement Part
Statement Part
Analogous to conventional
programming languages
process (sensitivity
list)
declaration part
begin
statement part
end process;
Example
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ha_beha_en is
port(
A : in BIT; B : in BIT; S : out BIT; C : out BIT );
end ha_beha_en;
architecture ha_beha_ar of ha_beha_en is
begin
process_beh:process(A,B)
begin
S<= A xor B;
C<=A and B;
end process process_beh;
end ha_beha_ar;
Structural modeling
Signal declaration.
Component instances
Port maps.
Wait statements.
Component declaration
Syntax:
component component_name [is]
List_of_interface ports;
end component component_name;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;
architecture fa_ar of fa_en is
component ha_en
port(A,B:in bit;S,C:out bit);
end component;
signal C1,C2,S1:bit;
begin
HA1:ha_en port map(A,B,S1,C1);
HA2:ha_en port map(S1,Cin,SUM,C2);
CARRY <= C1 or C2;
end fa_ar;