Professional Documents
Culture Documents
and Classification
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi
S3
f: I S O
o(t) = f(i(t), s(t))
g: I S S
s(t+1) = g(i(t), s(t))
f: S O
o(t) = f(s(t))
g: I S S
s(t+1) = g(i(t), s(t))
• Equivalent states
• Distinguishable states
• k-equivalent states
• k-distinguishable states
S1
0/1
Sik+1
Si Si 1
Sj Sj1 Sjk+1
S0 S1 1/0 b
0/0
0/0 1/0 0/0 1/0 0/0
1/1
S00 S10 S01 S11 c
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi
S0 S00/0
1/0 1
1/1 1
S1 S11/1
0/1 0
Chapter 3: Sequential Circuits 24
Equivalent Machines:
Waveforms
Clk
Mealy S0 S1 S1 S1 S0
State Encoding
0/1
0/1 AD
1/0 AD 00
X/0
1/1
C
B B 01
C 10
Chapter 3: Sequential Circuits 29
State Machine Realization
(contd.)
X PS NS Excite (T) Y
0 00 01 01 1
1 00 10 10 0
X 01 00 01 0
0 10 00 10 1
1 10 01 11 1
x y
Comb
Logic
T1
T2
D Q
Clk
Chapter 3: Sequential Circuits 34
Register & Latch Waveforms
Clk
Level
Edge
LD/EN LD OE
T Q TQ TQ T Q
Clk
Q0
Q1
Chapter 3: Sequential Circuits 38
Ripple Counter
• Advantages
– Simple low cost design
– High speed operation possible if outputs are not
required to be synchronous
• Disadvantages
– Delay = no. of bits flip-flop delay
– Illegal transient states
T Q TQ TQ T Q
Clk
Q0
Q1
Chapter 3: Sequential Circuits 40
Faster Synchronous Counter
T Q TQ TQ T Q
Clk
Carry delay is spread over 16 clock cycles
D Q
Counter
Clk Clr En Ld
Synch Async
Count Dec 9 Count Dec 10
Clr Clr
State Encoding
0/1
0/1 A
1/0 A 00
X/0
1/1
C
B B 01
C 10
Chapter 3: Sequential Circuits 45
State Machine Realization
(contd.)
X PS NS En, Clr, Ld D
0 00 01 100 X
1 00 10 001 10
X 01 00 010 X
0 10 00 010 X
1 10 01 001 01
x y
Comb
Logic
D En, Clr, Ld
C
N
Q T
(PS)
1 X X X X 0
0 1 X r D D
0 0 1 r X Q(t) +1
S255 S1 B
1/0
1/0
S2 C
1/1
0/0
0/0
D
Chapter 3: Sequential Circuits 54
Example (Contd.)
y
M1 M2
Clk
M1 Clr M2 y
Logic +
8-bit Cntr 2-bit Cntr
Clk
Clk
Mod256
x Comb y
Logic
PS NS
SR
Clk
tsu th
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi
Address
SRAM Data
rd/wr
cs
Adr
Rd/wr
Data
DBUS
ADBUS RO
Adr RAM
RI
Rd/Wr
Chapter 3: Sequential Circuits 67
Reading Memory in a SM
S1 Inc_Adr
En_Adr_src
S2
Ld_Dat_Reg
S1
Adr
S2
Data
S3
Wr
Chapter 3: Sequential Circuits 69
Dynamic RAM Device Signals
Address
Data_out
ras
cas SRAM
Data_in
rd/wr
cs
Adr
ras
cas
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi
Status
signals
Data Control
Part Part
Control
signals
x z
GCD
y
Computer
R1 R2
Comp R3 SUB
S1
S2
S5 S4 S3
x z
GCD
y
Computer
start eoc
add
delete
Chapter 3: Sequential Circuits 81
FIFO: Data Part
Head Memory
Tail
f e
S0
S3 S1
S4 S2
Chapter 3: Sequential Circuits 83