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Terminology
analog: continuously valued signal, such as temperature or
speed, with infinite possible values in between
digital: discretely valued signal, such as integers, encoded in
binary
analog-to-digital converter: ADC, A/D, A2D; converts an analog
signal to a digital signal
digital-to-analog converter: DAC, D/A, D2A
An embedded systems surroundings typically involve many
analog signals.
Analog-to-digital converters
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
1.5V
1.0V
0.5V
0V
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
proportionality
7.0V
6.5V
6.0V
5.5V
Vmax = 7.5V
t1
0100
t2
t3
t4
time
analog to digital
Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
t1
t2
0100
t3
1000 0110
Digital input
digital to analog
t4
time
0101
Proportional Signals
Simple Equation
Vmax
1..1 = 2n-1
d = digital encoding
a / Vmax = d / M
0V
0..0 = 0
Resolution
Let n = 2
Vmax
3=11
M = 2n 1
3=11
2=10
2=10
M = 2n
4 steps on the digital scale
d0 = 0 = 0b00
dVmax - r = 3 = 0b11 (no dVmax )
r, resolution: smallest analog change
resulting from changing one bit
1=01
1=01
0V
0=00
0=00
x0
x1
Vmax
DAC
Xn-1
ADC:
Given a Vmax analog input and an analog input a, how does the
converter know what binary value to assign to d in order to
satisfy the ratio?
2.
(5.05 + 4.93) =
4.99 volts
Constructing ADC
Analog
input
Vmax
Vmin
Comparator
State
machine
Timing
control
DAC
SAR
BUF
SAR
SAR: Successive
approximation register
Digital
output
Bit Weight
Notice the concept of bit weight
in the last example:
bit 7 = 7.5 V = 15/2
bit 6 = 3.75 V = 15/4
Digital Bit
10/2 = 5
10/4 = 2.5
10/8 = 1.25
10/16 = 0.625
10/32 = 0.313
10/64 = 0.157
10/128 = 0.078
10/256 = 0.039
Bit Weight
Example (continued): -5 V to
+5 V analog range, n=8
Digital numbers for a few analog
values
Analog (V)
Digital (hex)
-5
00
-3.75
20
-2.5
40
-1.25
60
80
1.25
A0
2.5
C0
3.75
E0
5-0.039 = 4.961
FF
MPC555 QADC64
QADC64 - Queued
Analog to Digital
Converter Module-64
16 analog channels via
internal multiplexing
10-bit ADC resolution
Converts voltage to an
integer value (0-1023)
Polling or interrupt driven
Programmable channels
AN0-ANx
MPC555 QADC64
MPC555 QADC64
CCW Table
CCW0
CCW1
AN0
AN1
AN2
AN3
CCW63
ADC
complete.
Result63
The ADC starts the scan and conversion when it is triggered by the
enable bit.
The ADC reads the CCWs, one after another until end-of-queue is
reached, and for each CCW, it converts the signal on the specified
channel.
A conversion on a channel stores a result in the respective position of the
Result Table, e.g., the result for CCW0 is stored at Result0, etc.
When the scan and conversion is complete for all CCWs, then the ADC
sets the completion flag to 1. Now all digital results are available to be
read from the Result Table.
QADC Interface
Programmability using a queue
Scan a few channels quickly
Scan a channel multiple times
Scan large number of channels
QADC Interface
CCW Table
o table of Conversion Command Words, where each command word specifies how
to perform a scan/conversion operation for an input channel
o CCW: 16 bit command word, starting at address 0x304A00
o A queue is a scan sequence of one or more input channels.
o A queue is started by a trigger event, which is a way to cause the QADC64 to
begin executing the command words.
o Each CCW requests the conversion of an analog channel to a digital result. The
CCW specifies the analog channel number, the input sample time, and whether
the queue is to pause after the current CCW.
CCW Table
Entry
00
16 bits
Begin Queue 1
0x304A00
0
5 6 7 8
9 10
IST
Reserved P BYP
MSB
n
End Queue 1
15
CHAN
LSB
QADC Interface
Total conversion time: initial sample time, final sample time, and resolution
time
o Initial sample time time during which the selected input channel is driven by
the buffer amplifier onto the sample capacitor (disabled by means of the BYP bit
in the CCW)
o Final sampling period time to set up DAC array
o Resolution period time to convert voltage in the DAC array to a digital value
QADC Interface
Result Word Table
o table of Result Words, where each result word is the digital result of a
conversion
o Results from a sequence of conversions are placed in the Result Word
Table.
o RW: 16 bit result word, starting at address 0x304A80
0x30 4A00
64-entry 16-bit Conversion
Command Word Table
(Configurable: one queue
or two queues)
0x30 4A7E
0x30 4A80
64-entry 16-bit
Result Word Table
64-entry, 16-bit
0x30 4AFE
Programming QADC64
CCW Format:
6
P
7
BYP
8 9 10 11 12 12 14 15
IST
CHAN
nChannel;
nQueueVal & 0xFF3F;
nQueueVal | 0x0040;
+ nQueue) = nQueueVal;
CF1
PF1
TOR1
Trigger over-run
QS
Queue status
CWP
Programming QADC64
Example: Reset QADC64 by writing END-OF-QUEUE (63 in decimal) as
the first word of CCW table.
void QADCR64_Reset()
{
g_nNumChannels = 0;
QADCR64_SetQueue(0, QADCR64_END_QUEUE,
QADCR64_QCKL_MAX);
}
QADCR64_SetQueue: Given CCW entry index, CCW channel/end-ofqueue command, and final sample setting, write the corresponding CCW.
Programming QADC64
Example: Start scanning in polling mode (interrupt disabled)
Set up control register 1
void QADCR64_Start_Convert_Poll ()
{
unsigned short * pQACR1;
pQACR1 = (unsigned short *) 0x30480C;
// Bit 0 CIE1 Conversion Interrupt Enable 0
// Bit 1 PIE1 Pause Interrupt Enable 0
// Bit 2 SSE1 Single Scan Enable 1
// MQ=00001; software triggered single scan mode
*pQACR1 = 0x2100;
}
Programming QADC64
Example: Determine if all conversions has finished
4 5
IRL1
9 10
IRL2
15
Reserved