3-Dimensional Integrated circuits

PRESENTED BY:
S.Deva

CONTENTS

WHAT IS 3-D IC?

INCENTIVES
LIMITED PERFORMANCE OF 3-D IC
3-D ARCHITECTURE
MANUFACTURING TECHNOLOGY OF 3D ICs
ADVANTAGES OF 3-D ARCHITECTURE
DISADVANTAGES OF 3-D ARCHITECTURE
PERFORMANCE CHARACTERISTICS
PRESENT SCENARIO IN 3-D IC INDUSTRY
CONCLUSION

What is a 3D
3D Integrated circuit is a chip which accommodates two or more layers
of active electronic componentsIC??
They are integrated both horizontally and vertically onto a single
circuit.

INCENTIVES:
To reduce wastage of space on the substrate.
To improve interconnections among different wafers.
To reduce the length of interconnections which in turn reduces heat
dissipation and also RC delays.
Can be used to accommodate both homogenous and heterogeneous chips.
Thus there is a great urge to switch over from 2D ICs to 3D ICs

LIMITED PERFORMANCE OF 3D ICs

As we try to increase the performance and efficiency of

chip, the complexity of chip design increases and this requires
more and more transistors. So the final size of the circuit and
delays increases.

The losses increases with large interconnection because the

capacitance and resistances are generated in between the clad
and copper.

3D IC ARCHITECTURE
3D IC is a concept that can significantly :

Improve interconnect performance,

Increase transistor packing density,
Reduce chip area
Reduce Power dissipation

In 3D design structure the entire chip Si is

divided by number of layers of oxide and metal,
to form transistors.

MANUFACTURING TECHNOLOGY OF 3D ICs

There are four ways to built 3D ICs :1.

Monolithic

2.

Wafer on wafer

3.

Die on wafer

4.

Die on die

1. Monolithic
Electronic components and their connections (wiring) are
built in layers on a single semiconductor wafer, which is then
diced into 3D ICs.
There is only one substrate, hence no need for aligning,
thinning, bonding, or through-silicon vias.

2. Wafer on wafer
Electronic components are built on two or more semiconductor wafers,
which are then aligned, bonded, and diced into 3D ICs.

3. Die on wafer
Electronic components are built on two semiconductor wafers. One wafer is
diced aligned and bonded onto die sites of the second wafer.

4.Die on die
Electronic components are built on multiple dice, which are then aligned
and bonded.
One advantage of die-on-die is that each component die can be tested
first, so that one
bad die does not ruin an entire stack

PERFORMANCE CHARACTERISTICS

1.

TIMING

2.

ENERGY

With shorter interconnects in 3D ICs, both switching

energy and cycle time are expected to be reduced

Timing performance:
In current technologies, timing is interconnect driven.
Reducing interconnect length in designs can dramatically reduce RC delays and increase
chip performance
The graph below shows the results of a reduction in wire length due to 3D routing

Energy performance:
Wire length reduction has an impact on the cycle time and the energy dissipation
Energy dissipation decreases with the number of layers used in the design

PRESENT SCENARIO IN 3D IC INDUSTRY

Many companies like MIT (USA), IBM are doing research on 3D IC technology
and they are going to introduce cheaper chips for certain applications, like
memory used in digital cameras, cell phones, handheld gaming devices etc.
The original cost will be 10 times lesser than the current ones.

3D integration can reduce the wiring, thereby reducing the capacitances, power
dissipation and chip area improves performance.
Digital and analog circuits can be formed with better noise performance.
Cost is more effective than 2D integration.
ADVANTAGES :

DISADVANTAGES :
Higher cost Drill holes
Thinning
Handling/Align
2 types of die (Master and Slave)

Applications:
physical limitations for classic 2D electronics
addressing all important issues, such as wafer
processing
applications of mixed signal designs.

CONCLUSION
3D ICs will be the first of a new generation of
dense, inexpensive chips having less delay and
interconnection losses that will replace the
conventional storage and recording media.

Any
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