MOS FET

Overview
Triode region
Saturated region
CMOS
BiCMOS

Overview of MOS

Metal-oxide semiconductor (MOS) integrated circuits (ICs) have

become the dominant technology in the semiconductor industry
With MOS, it is possible to have a lot of millions of transistor on a
single chip
It allows the fabrication of a complete 64-bit microprocessor or
some Gbyte memory
The main reason is that MOS ICs exceed the bipolar transistors:
in functional density (the number of functions performed on a single
chip),
MOS transistors are simpler to fabricate

What is a MOS Transistor?

MOS transistor consists of semiconductor material (silicon) on

which is grown a thin layer (1...50 nm) of insulating oxide, topped
by a gate electrode
The gate electrode was originally metal, specifically aluminium,
but is now more commonly a layer of polycrystalline silicon
(referred to as polysilicon)
Source and drain pn-junctions are formed with a small overlap
with the gate

MOS Capacitor

The metal oxide semiconductor (MOS) capacitor is at the core of the complementarymetal-oxide-silicon (CMOS) technology. Silicon metal-oxide-silicon-field-effecttransistors (MOSFETs) rely on the extremely high quality of the interface between
SiO2, the standard gate dielectric, and silicon. Before we begin our discussion on the
MOSFET, it is essential to achieve a satisfactory understanding of the MOS capacitor
fundamentals.

Metal Oxide Semiconductor Field

Effect Transistor
The MOSFET shown in the adjacent figure is an nchannel MOSFET, in which electrons flow from
source to drain in the channel induced under the gate
oxide. Both n-channel and p-channel MOSFETs are
extensively used. In fact, CMOS IC technology relies
on the ability to use both devices on the same chip.
The table below shows the dopant types used in each
region of the two structures.

Simplified Schematic of a MOSFET

Substrate (Channel)
Gate Electrode
Source and Drain

n-channel MOSFET
p
n+
n+

p-channel MOSFET
N
p+
p+

Metal-Oxide-Semiconductor Transistors

Most modern digital devices use MOS transistors, which have two advantages over other types
greater density
simpler geometry, hence easier to make

MOS transistors switch on/off more slowly

MOS transistors consist of source and drain diffusions, with a gate that controls whether the transistor is on

Gate

n+

D
n+

metal
silicon
dioxide
monosilicon

Device: The MOS Transistor

Gate oxide
Polysilicon
Gate
Source
n+

Drain
n+
p substrate

Bulk contact
CROSS-SECTION of NMOS Transistor

Field-Oxide
(SiO2)
p+ stopper

Anatomy of a
MOS FET

Adding certain types of impurities to the silicon in a transistor

changes its crystalline structure and enhances its ability to conduct
electricity
Silicon containing boron impurities is called p-type silicon
p for positive or lacking electrons
Silicon containing phosphorus impurities is called n-type silicon
n for negative or having a majority of free electrons

MOS Transistor
Transistors consist of three
terminals; the source, the gate,
and the drain

In the n-type transistor, both the

source and the drain are negativelycharged and sit on a positivelycharged well of p-silicon

MOS Transistor
When positive voltage is applied to the gate,
electrons in the p-silicon are attracted to the area
under the gate forming an electron channel between
the source and the drain

When positive voltage is applied to the drain,

the electrons are pulled from the source to the
drain. In this state the transistor is on

MOS Transistor
If the voltage at the gate is removed,
electrons aren't attracted to the area
between the source and drain
The pathway is broken and the transistor
is turned off
The binary function of transistors gives micro-processors the ability to
perform many tasks
from simple word processing to video editing
Microprocessors have evolved to a point where transistors can execute
hundreds of millions of instructions per second on a single chip
Automobiles, medical devices, televisions, computers, and even the
Space Shuttle use microprocessors
They all rely on the flow of binary information made possible by the
transistor

The MOS Device (3D structure)

Contacts

Poly on thin
Gate oxide

Metal 1

N+ Implant

.18m technology (hcmos8)

Basic n-MOS technology

Physical Structure of MOS FETS

NMOS

PMOS

[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]

2D Representation of MOS Transistor

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB ]

Device Operation Schematic

Figure shows an n-channel MOSFET
with voltages applied to its four
terminals. Typically, VS = VB and VD >
VS. For simplicity, we assume that the
body and the source terminals are tied
to the ground, ie. VSB=0. This yields

VGS VGB VSB VGB VG

VDS VDB VSB VDB VD

I-V Characteristics

Linear

As shown, at low VDS, the drain current increases almost linearly with VDS, resulting in a
series of straight lines with slopes increasing with VGS. At high VDS, the drain current
saturates and becomes independent of VDS.

Regions of MOSFET Operation

Off-State Region
With a small positive voltage on the drain and
no bias on the gate
i.e. VDS > 0 and VGS = 0, the drain is a reverse
biased pn junction
Conduction band electrons in the source region
encounter a potential barrier determined by the
built-in potential of the source junction
As a result electrons cannot enter the channel
region and hence, no current flows from the
source to the drain
This is referred to as the off state

Linear Region
With a small positive bias on the gate, electrons can enter the channel and a current
flow from source to drain is established
In the low drain bias regime, the drain current increases almost linearly with drain
bias
Indeed, here the channel resembles an ideal resistor obeying Ohms law
The channel resistance is determined by the electron concentration in the channel,
which is a function of the gate bias
Therefore, the channel acts like a voltage controlled resistor whose resistance is
determined by the applied gate bias
As the gate bias is increased, the slope of the I-V characteristic gradually increases
due to the increasing conductivity of the channel
We obtain different slopes for different gate biases
This region where the channel behaves like a resistor is referred to as the linear
region of operation
The drain current in the linear regime is given by
I D ,lin

W
1 2

Cox VGS VT VDS VDS

L
2

Saturation Region
For larger drain biases, the drain current saturates and becomes independent
of the drain bias
Naturally, this region is referred to as the saturation region
The drain current in saturation is derived from the linear region current,
which is a parabola with a maximum occurring at VD,sat given by
VD,sat

VGS VT

To obtain the drain current in saturation, this VD,sat value can be substituted
in the linear region expression, which gives
I D , sat

V VT
W
GS
Cox
L
2

Saturation Region I

Saturation Region I

As VDS is increased, the number of electrons in the inversion layer

decreases near the drain due to
a) since both the gate and the drain are positively biased, the potential
difference across the oxide is smaller near the drain end
Since the positive charge on the gate is determined by the potential drop
across the gate oxide, the gate charge is smaller near the drain end
This implies that the amount of negative charge in the semiconductor
needed to preserve charge neutrality will also be smaller near the drain
Consequently, the electron concentration in the inversion layer drops

b) increasing the voltage on the drain increases the depletion width

around the reverse biased drain junction
Since more negative acceptor ions are uncovered, a fewer number of
inversion layer electrons are needed to balance the gate charge
This implies that the electron density in the inversion layer near the drain
would decrease even if the charge density on the gate was constant

Saturation Region II

The reduced number of carriers cause a reduction in the channel

conductance which is reflected in the smaller slope of IDS - VDS
characteristics as VDS approaches VD.sat and the MOSFET enters the
saturation region
Eventually, the inversion layer completely disappears near the
drain
This condition is called pinch-off and the channel conductance
becomes zero
The VDsat increases with gate bias
This is due to the fact that a larger gate bias requires a larger drain
bias to reduce the voltage drop across the oxide near the drain end

Saturation Region III

As VDS is increased beyond VD,sat, the width of the pinched-off

region increases
However, the voltage that drops across the inversion layer remains
constant and equal to VD,sat
The portion of the drain bias in excess of VD,sat appears across the
pinch-off region
In a long channel MOSFET, the width of the pinch-off region is
assumed small relative to the length of the channel
Thus, neither the length nor the voltage across the inversion layer
change beyond pinch-off resulting in a drain current independent
of drain bias
Consequently, the drain current saturates

Saturation Region IV

From the above discussion it is also evident that the

electron distribution is highest near the source and
decreases near the drain
To keep a constant current throughout the channel, the
electrons travel slower near the source and speed up near
the drain
In fact, in the pinch-off region, the electron density is
negligibly small
Therefore, in this region, in order to maintain the same
current level, the electrons have to travel at much higher
speeds to transport the same magnitude of charge

NMOS & PMOS

In the n-channel transistor the semiconductor body (or substrate)

is p-type and the source and drain diffusions are p-type
In the discussion we shall use n-channel transistors (NMOS) for
our analysis
The NMOS conducts via electrons

The analysis for p-channel transistor (PMOS) follows simply by

invoking duality
all semiconductor types are reversed
polarity of applied voltages are reversed
The PMOS conducts via holes by reversing all applied voltage
polarities and semiconductor types

NMOS Operation

With no voltage applied to gate, there is no conduction path

between the source and drain
When a voltage, positive with respect to the substrate, is applied
to the gate and is of such a magnitude that it is greater then a
certain threshold voltage VT, then electrons are attracted to the
surface of the semiconductor
Electrons are minority carriers in the p-type substrate

In fact, so many electrons are attached to the surface that an

extremely thin (5 nm) channel is formed, where the semiconductor
actually changes from p- to n-type

Transistor Gain

Now, when a voltage is applied between source and drain, current

can flow
The current flow is via majority carriers, since electrons flow
through all n-type materials
Transistor gain results from the ability of the gate voltage to
modulate the channel conductivity
The electrons pile up at the oxide-semiconductor interface (i.e., the
silicon surface) rather than flow through the gate circuit because
the gate oxide prevents any dc gate current from flowing

Enhancement- & Depletion-mode

Transistor

The NMOS device requires a voltage to be applied before the

channel is formed and is called an enhancement-mode transistor
sometimes, when there are built-in positive charges at the oxidesemiconductor interface or when charges are deliberately
introduced by ion implantation, a channel will be formed even
when no gate voltage is applied
Such a transistor is called a depletion-mode transistor, because a
reverse polarity (in the case of NMOS, negative) gate voltage would
have to be applied to deplete the channel of electrons and shut the
device off
Its threshold voltage is thus negative
The depletion-mode n-channel devices still conduct vie electrons

Terminals

MOS transistors are always four-terminal devices

In most applications, the substrate is often tied to the source

MOSFET vs. BJT

drain

body

collector

base

gate

source
n-channel MOSFET

emitter
npn bipolar transistor

MOS Transistor Transfer Characteristics

If one ties the substrate to the source, then the transfer

characteristics (drain current versus drain-to-source voltage) of a
MOS transistor is the so-called transfer characteristics
Fro a given applied gate voltage that is greater than the threshold
voltage, the drain current will rise increasing drain-to-source
voltage
However, the rate of rise decreases until the drain current soon
saturates to a constant value
At a higher gate voltage, the same shaped curve will result except the
current values will be higher

There are two regions in the transfer characteristics plot:

triode (linear) region
saturation region

Triode (Linear) Region

Current is rising, the drain current is described by

1

I D (VGS VT )V DS V DS 2 , if V DS VGS VT
2

W
KN
is a cons tan t
L

In case of relatively small drain-to-source voltage the second term

can be eliminated

Saturation Region

In this region the drain current does not depend on drain-to-source

voltage:
1
I D (VGS VT ) 2 , if V DS VGS VT
2
W
KN
is a cons tan t
L

The point where the two lines meet is at the saturation drain
voltage:
V DS V DS ,sat VGS VT

Typical values
A

In case of NMOS : K K N 16
, VT 1 V ,
2
V
A
In case of PMOS : K K P 8
, VT 1 V
2
V
Typical value: W 1
L
100

In case of NMOS the drain voltage is more positive, in case of

PMOS the drain voltage is more negative than the other electrode

MOS Transistors (continued)

Making gate positive (for n channel device) causes current to flow from source to drain
attracts electrons to gate area, creates conductive path

For given gate voltage, increasing voltage difference between source and drain increases current from
source to drain

n+

n+
p

+
-

Basic NMOS Construction

MOSFET Symbols
drain
gate

drain
body

source

gate

A circle is sometimes
used on the gate terminal
to show active low input

or
drain

source
or
drain

body

gate

body

source
A) n-channel MOSFET

body

gate
source

B) p-channel MOSFET

Complementary MOS Transistors

(CMOS)

If one were to fabricate PMOS and NMOS devices on the same

substrate to build complementary MOS (CMOS) circuits, there
would be a basic inconsistency in substrates
This is solved by using a p-tub diffusion to create the background
for the n-channel devices
VDD
p

Y = A'
n
GND

CMOS

A variant of MOS transistor uses both n-channel and p-channel

devices to make the fundamental building block
as inverter = not gate
Its advantages:
lower power consumption
symmetry of design
If in = +, n-channel device is on, p-channel is off, out is
connected to If in = -, n-channel is off, p-channel is on, out is connected to +
No current flows through battery in either case
P
i
n

ou
t

Basic CMOS Logic Technology

Based on the fundamental inverter circuit

Transistors (two) are enhancement-mode MOSFETs
N-channel with its source grounded
P-channel with its source connected to +V

Input: gates connected together

Output: drains connected

Ideal Structure of a CMOS Intverter

CMOS geometry (and manufacturing process) is more complicated than

the NMOS

n+

n+

S
p+

p+

Real Structure of a CMOS Inverter

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

BiCMOS Technology

Bi-CMOS combines CMOS and bipolar (another transistor

type) on one chip

CMOS for logic circuits
Bi-polar to drive larger electrical circuits off the chip