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Basic Model
Processing speed or program execution
determined primarily by ability of I/O
operations to stay ahead of processor.
Input
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Process
Output
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I/O Considerations
Speed Issues
CPU operates at speeds much faster than the fastest I/O device
Devices operate at different speeds
Bursts of data
Block data transfer required for some devices
Coordination
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parallel interface
serial interface
Buffering of data
Burst vs. stream
Different control requirements
electromechanical
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Input/Output Modules
Programmed I/O
CPU controlled I/O
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Programmed I/O
I/O data and address registers in CPU
One word transfers
Address information for each I/O device
LMC I/O capability for 100 devices
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Programmed I/O
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Interrupts
Signal that causes the CPU to alter its
normal flow on instruction execution
frees CPU from waiting for events
provides control for external input
Examples
unexpected input
abnormal situation
illegal instructions
multitasking, multiprocessing
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Execute
Instruction
Interrupts Disabled
Check/Process
Interrupt
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Interrupt Terminology
Interrupt lines (hardware)
Interrupt request
Interrupt handlers
Program that services the interrupt
Also known as an interrupt routine
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Interrupt Terminology
Servicing the interrupt
suspends program in progress
saves pertinent information including last
instruction executed and data values in
registers in the PCB (process control
block)
branches to interrupt handler
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Servicing an Interrupt
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Use of Interrupts
Notify that an external event has occurred
real-time or time-sensitive
Signal completion
printer ready or buffer full
Software interrupts
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Multiple Interrupts
Identifying devices
Polling (checking for input in rotation)
Vectored interrupts (include address of
interrupting device)
Interrupt priorities
Loss of data vs. task completion
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Vectored Interrupts
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Polled Interrupts
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privileged instructions
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Bus Configuration
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Bus Characteristics
Data width in bits carried simultaneously
Throughput, i.e., data transfer rate in bits
per second
Point-to-Point vs. Multipoint
Parallel vs. Serial
Use
Distance
Protocol
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Bus Hierarchy
Processor bus: on-chip
Cache bus (backside bus)
Memory bus (front-side bus)
connects the memory subsystem and processor
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SCSI
Small Computer System Interface
USB, USB-2
Universal Serial Bus
IEEE 1394
Firewire
i.link
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SCSI Bus
ANSI standard but multiple variations
Really an I/O bus rather than simple interface
Supports multiple devices from a single SCSI port
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USB
Multipoint bus
Hubs provide
multiple connection
points for I/O devices
Supports 127 devices
Topology Example
Root
Hub
Hub
Hub
Hub
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Channel Architecture
Used in IBM mainframe computers
Channel subsystem
Separate I/O processor that serves as a CPU for
I/O operations
Channel control words
Programs that transfer data between memory and
an I/O device using DMA
Subchannels
Connected to a control unit module through one or
more channel paths
Similar role to a device controller
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