Professional Documents
Culture Documents
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Verilog HDL
Coding for Simulation &
Synthesis
Whats Coming
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Objectives
Introduce Verilog language concepts
Use of language features to capture hardware design
specification and Verify
Explore gate level modeling capabilities
Understand PLI capability
Format
Morning Presentations
Afternoon Lab Exercises
Timing
Coffee..10.30 to 10.45 & 3.30 to 3..45
Lunch1.00 to 2.00
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Part-I
Designing using Verilog ( RTL Coding )
SCHEDULE
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- Session I
Introduction to Verilog-HDL, Data Types, Operators.
Verilog Language Concept, Hierarchy, Concurrency,
Timing
Continuos and Procedural Assignments
- Session II
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SCHEDULE
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- Session I
Verilog Coding styles RTL , Behavioural.
Sequential statements - if else, case, for loop, while loop,
statements
Blocking and Non-blocking statements,Simulation cycle
- Session II
Lab 2
Sequential Logic exercises- Registered logic, timing
logic, Counting logic..
Assignments
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SCHEDULE
- Session I
Synthesis Process
Structural RTL coding
- Session II
Lab 3
Coding for Finite State Machines
Assignments
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SCHEDULE
- Session I
Sample complete design
RTL coding Guidelines
- Session II
Lab 4
Use of External IP in design
Structural coding
Assignments
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Part-II
Verification using Verilog ( Behavioral Coding )
SCHEDULE
- Session I
- Session II
Lab 1- Use of Simulation and synthesis Tools
Writing Simple Test benches for Multiplexer,
comparator,Decoder..
Writing Test bench for Clocked logic
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SCHEDULE
- Session I
Tasks & Functions
PLI Overview
Creating PLI applications
- Session II
Lab 2
Writing test benches using Tasks
Writing test benches for FSMs
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SCHEDULE
- Session I
Sum up
- Session II
Lab 3
Writing structured test benches using I/O files
Complete verification of structured model
Design Debugging
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Verilog Application
Verilog Application
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Objectives
Identify the advantages of designing with an HDL.
Applications of Verilog
Define what is meant by levels of abstraction with
respect to:
Verilog modeling
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What is Verilog
Verilog is not a software
language
Verilog is a Hardware
Description Language (HDL)
Programming language with
special constructs for modeling
hardware
Hardware behavior
Serial (sequential)
Concurrent (parallel)
Structure
a
b
r Behavior
Tpd
Timing
Abstraction levels
D Q
clk
Tnet
Tsetup
Thold
Tclk-q
Timing
Levels of Abstraction
Behavioral
algorithmic
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Register
Transfer Level
Logic synthesis
Verilog
Gate level
-structural
-netlist
Physical
-silicon
-Switch
Layout / place
& Route
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op
data
2
4
data
4
op
SLI
clk
D Q
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Applications
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Testbench
behavioral
Design
RTL
Compare
Results
Expected
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Contents
Verilog objects
Verilog connection model
Hierarchy
Rules and regulations
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module
Describes interface and
behavior
Modules communicate
through ports
Port names listed in
parentheses after the
module name.
Ports can be defined as
input, or inout (bidirectional)
^is the exclusive or operator
& is an logical and operator
Important to Remember :
Verilog is case sensitive for
identifiers keywords must be
in lowercase
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= a^b
= a&b
endmodule
halfadd
a
b
sum
+
carry
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Representing Hierarchy
Create hierarchy by
Instantiating module
Connecting module ports to
local ports or nets
Local nets need to be
declared
The or construct is a built
in gate primitive
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fulladd
n_sum
a
b
cin
U1
halfadd
U2
sum
n_carry2
halfadd
n_carry1
carry
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n_sum
a
b
n_carry1
module
a sum
b carry
U1
endmodule
halfadd
mapped to
wire n_carry1
of fulladd module
Tip
Output carry of
halfadd module
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instantiation
endmodule
n_sum
n_carry1
U1
module
a sum
b carry
halfadd
Caution
Less readable and more error-prone
than named port connection
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initial procedure
Executes once at start of
simulation
Used for initialisation,
testbenches
Synthesis
initial blocks are not synthesisable
always @ (a or b or sel)
if (sel = = 1)
y=a;
event list
else
y=b;
1
y
b
sel
0
initial
begin
a = 1;
b = 0;
end
Event List
always procedure
executes when one or
more variables in the
event list change
value
An event is a change
in logic value
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Procedure
Procedure
Procedures contained in
a module
Procedure
Compilation Library
WORK
MY_WORK
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a_clk.v
PRIMS
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PROJ
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Design Compilation
Design compiled from a list
tb_one
testbench
design
structural
cpu
behavioral
pnet_read
RTL/structural behavioral
read_frame
netlist
pnet_write
write_frame
primitives
of Verilog files
Normally compile the
testbench first
Usually contains
compiler directives
Provides additional
information for the
compiler/simulator
Order of other files generally
not important
Hierarchical connections are
automatically made
Verilog allows different levels
of abstraction anywhere in
the hierarchy
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unit_32
structural
bus_16_bite
a$b
unit@32
unit - 32
16_bit_bus
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Aims
To introduce the Verilog logic value system and to
understand the different data types and the rules
covering their use.
Topics
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buf
One,High,True,Logic High,
Power, VDD, VCC, Positive
Assertion
buf
X
bufifI
Important
The unknown logic value x is not the same as dont care.
Data Types
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Registers
Represent abstract storage elements e.g.reg
Parameters
Run-time constants
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Net
Types
A Net type behaves like a wire driven by a logic gate
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//
//
//
//
Scalar wire
Two 32-bit wires with msb = bit 31
Scalar wired-AND net
A 16-bit tri-state bus, msb = bit 15
module halfadd (a, b, sum, carry) ;
input a, b;
// default to wire
output sum, carry ;
// default to wire
// change with assign
assign sum = a ^ b;
assign carry= a & b;
endmodule
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nsela
sel
out
nsel
b
selb
Nets
module mux (a, sel, b, out);
input sel, b, a;
output out ;
wire nsela, selb, nsel ;
assign nsel = ~sel;
assign selb = sel & b ;
assign nsela = nsel & a;
assign out = nsela | selb ;
endmodule
= nsela | selb;
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a
?
assign y = a ;
assign y = b ;
b
y declared as
wand y ;
triand y ;
y declared as
wor y ;
trior y ;
b
b 0 1 x z
a
0 1 x z
a
a 0 1 x z
0 0 x x 0
0 0 0 0 0
0 0 1 x 0
1 x 1 x 1
1 0 1 x 1
1 1 1 1 1
x x x x x
x 0 xx x
x x 1 x x
z 0 1 x z
z 0 1 x z
z 01 x
x
Synthesis wire and tri are synthesisable,
some synthesis tools support wor and wand
b
Register Types
Register types stores value until a
new value is assigned
Various register types are available
reg is the most commonly used
Register values changes with
procedural assignment
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always @ (a or b or sel)
begin
if (sel = = 1)
op = a;
Synthesis
else
reg and integer are synthesisable, but do not
op = b;
have to synthesis to a flip-flop in hardware
end
endmodule
Register types:reg
reg [3:0] vect ;
// 4-bit unsigned vector
reg [2:0] p, q ;
// two 3-bit unsigned vector
integer
integer i ;
// 32-bit signed integer
real
reg s ;
// unsized reg defaults to 1-bit
time
time delay ;
// time value
Register Assignment
module mux ( a, b, c, sel, mux ) ;
Register types can only be
updated from within a
procedure
Procedures can only update
register types
Registers and nets can be mixed
on the right-hand-side of an
assignment
Error
Net type assigned
in procedure
Error
Register type
assigned outside
procedure
input a, b, c ;
input sel ;
output mux ;
wire aandb, nmux ;
reg mux, nota ;
always @ (a or b or sel)
if (sel = = 1)
begin
mux = a ;
nmux = b ;
end
else
begin
mux = a ;
nmux = b ;
end
assign nota = ~a;
assign aandb = a & b ;
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net/register
atop
btop
Input Port
net
a
b
module top;
wire ytop;
reg atop, btop;
initial
begin
atop = 1b0;
btop = 1b0;
end
dut U1 (.a(atop), .y(ytop), .
b(btop));
endmodule
Output Port
net/register
net
y
Inout Port
net
ytop
net
module dut (y, a, b) ;
output y;
input a, b;
assign y = a&b;
endmodule
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Parameters
// parameter list
parameter pl = 8,
REAL_p = 2.039,
X_WORD = 16bx ;
module mux (a, b, sel, out) ;
parameter WIDTH = 2;
input [WIDTH 1:0] a;
input [WIDTH 1:0] b;
input sel ;
output [WIDTH 1:0] out ;
reg
[WIDTH 1:0] out ;
always @ (a or b or sel)
if (sel)
out = a;
else
out = b;
endmodule
module muxs (abus, bbus, anib, bnib, opbus, opnib, opnib1, sel );
parameter NIB = 4:
input [NIB-1:0] anib, bnib;
input [7:0] abus, bbus;
input sel;
Example follows..
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Generic Decoder
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parameter sizein=3,
sizeout=8;
input ena;
input en;
input [sizein-1:0]a;
output [sizeout-1:0]y;
reg [sizeout-1:0]y;
integer i;
always @(en or a)
begin
if(!en)
y=0;
else
if(a > sizeout-1 )
for (i=0;i<= sizeout-1;i=i+1)
y[i]=1'bx;
else
for (i=0;i<= sizeout-1;i=i+1)
if(a==i)
y[i]=1;
else
y[i]=0;
end
endmodule
input enb;
input [1:0]adda;
input [1:0]addb;
output [3:0]decadda;
output [3:0]decaddb;
gen_dec#(2,4) dec2_4(ena,adda,decadda);
gen_dec #(3,8) dec3_8(enb,addb,decaddb);
endmodule
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Summary
A net type behaves like a real wire driven by a logic gate
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Verilog Operators
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Aims
-Introduce the operators available in the Verilog language
Topics
Operator Type
Symbol
arithmetic
bit-wise
logical
reduction
shift
relational
equality
conditional
concatenation
replication
+-*/ %
~& ^~^
!&&
& ^ ~ & ~ ~ ^
<< >>
< > <= >=
== != === !=
=
?:
{}
{{ }}
Arithmetic
Operators
module arithops ( ) ;
+ add
*
/
%
substract
multiply
divide
modulus
Binary arithmetic is
unsigned
Integer arithmetic is
signed
Synthesis
% not synthesisable
/ only synthesisable if dividend
is a power of 2
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Bit-Wise Operators
~ not
& and
or
^ xor
~ ^ xnor
^ ~ xnor
Bit-wise operators
operate on vectors.
Operations are
performed bit by bit
on individual bits.
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module bitwise ( ) ;
reg [3:0] rega, regb, regc ;
reg [3:0] num ;
initial
begin
rega = 4 b1001 ;
regb = 4 b1010 ;
regc = 4 b11x0 ;
num = ~rega;
// num
num = rega & 0 ; // num
num = rega ®b; // num
num = rega | regb; // num
num = regb & regc; // num
num = regb | regc; // num
end
endmodule
=
=
=
=
=
=
0110
0000
1000
1011
10x0
1110
Note: Unknown bits in an operand do not necessarily lead to unknown bits in the result
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parameter FIVE = 5;
reg ans ;
reg [3:0] rega, regb, regc ;
initial
begin
rega = 4b0011; // reduces to 1
regb = 4b10xz; // reduces to 1
regc = 4b0z0x; // reduces to x
ans = ! rega;
// ans = 0
ans = rega && 0;
// ans = 0
ans = rega | | 0;
// ans = 1
ans = rega && FIVE; // ans = 1
ans = regb && rega ; // ans = 1
ans = regc | | 0;
// ans = x
end
endmodule
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module reduction ( ) ;
reg val ;
reg [3:0] rega, regb;
initial
begin
rega = 4b0100;
regb = 4b1111;
val = & rega ;
val = | rega ;
val = & regb ;
val = | regb ;
val = ^ rega ;
val = ^ regb ;
val = ~ | rega ;
val = ~ ®a;
val = ^rega && regb;
end
endmodule
// val = 0
// val = 1
// val = 1
// val = 1
// val = 1
// val = 0
// val = 0
// val = 1
// val = 1
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Shift Operators
> > shift right
< < shift left
Shift operators perform
left or right bit shifts on
the operand.
Shift is logical
0 is used for extra bits
Shifts can be used to
implement division or
multiplication by powers
of two
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module shift ( ) ;
reg [9:0] num ;
reg [7:0] rega ;
initial
begin
rega = 8b00001100;
num =rega >> 1; // num = 0000000110
num = rega >> 3; // num = 0000000001
num = rega << 5; // num = 0110000000
end
endmodule
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Relational Operators
> greater than
< less than
>= greater than or equal
<= less than or equal
The result is: 1b1 if the condition is true
1b0 if the condition is false
1bx if the condition cannot
be resolved
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module relationals;
reg [3:0] rega, regb, regc;
reg val ;
initial
begin
rega = 4b0011;
regb = 4b1010;
regc = 4b0x10;
val = regc
val = regb
val = regb
val = regb
end
endmodule
> rega ;
< rega ;
>= rega ;
> regc ;
// val = x
// val = 0
// val = 1
// val = x
Conditional Operator
module tribuf (in, enable, out);
? : conditional
in
out
enable
a
b
sel
out
wire out3;
reg out1, out2;
always @ (a or b or sel)
out1 = sel ? a : b ;
always @ (a or b or sel)
if (sel)
out2 = a;
else
out2 = b;
assign out3 = sel ? a : b;
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Concatenation
{ } concatenation
Allows you to select
bits from different
vectors and join them
into a new vector.
Used for bit
reorganization and
vector construction
e.g.rotates
Can used on either
side of assignment
Important
Literals used in concatenation
must be sized
module concatenation;
reg [7:0] rega, regb, regc, regd, new;
reg [3:0] nib1, nib2;
initial
begin
rega = 8 b00000011;
regb = 8 b00000100;
regc = 8 b00011000;
regd = 8 b11100000;
new = { regd [6:5], regc [4:3], regb[3:0];
// new = 8 b11_11_0100
new = {2 b11, regb[7:5], rega[4:3], 1 b1};
// new = 8 b11_000_00_1
new = {regd [4:0], regd[7:5]};
// rotate regd right 3 places
// new = 8b00000_111
{nib1, nib2} = rega;
// nib1 = 4 0000, nib2 = 4 0011
end
endmodule
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Replication
{ { } } replication
Replication allows you to
reproduce a sized variable a
set number of times
Can be nested and used
with concatenation
Syntax is:{ <repetitions> {<variable>} }
Important
Literals used in replication must be sized
4x rega concatenated
with 2x regc [1:0]
regc concatenated
with 2x regb
regc concatenated with 2x
1b1 and replicated 2 times
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module replicate ( ) ;
reg rega;
reg [1:0] regb;
reg [3:0] regc;
reg [7:0] bus;
initial
single bit rega
begin
replicated 8 times
rega = 1 b1;
regb = 2b11;
regc = 4 b1001;
bus = {8{rega}};
// bus = 11111111
bus = { {4{rega}}, {2{regc[1:0] }} };
// bus = 1111_01_01
bus = { regc, {2{regb}} };
// bus = 1001_11_11
bus = {2 {regc[2:1], {2{1b1}}} };
// bus = 00_1_1_00_1_1
end
endmodule
Operator Precedence
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Symbols
{} {{ }}
!
~
*
/
%
+
<<
>>
<
<=
> >=
==
!= === !==
&
~&
^
^~
~
&&
?:
Highest
Precedence
Lowest
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Procedural Statements
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Aim
To introduce some of the most commonly
used procedural statements
Topics
Procedures
Procedural statements
if then else
case
loops
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Procedural Assignments
Assignments made inside
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always @ (a or b or cin)
begin
sum = a ^ b ^ cin;
carry = ((a & b) | ( cin & (a ^ b)))
out
= {carry, sum};
end
endmodule
Event Control
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always @ (a or b or sel)
begin
if (sel = = 1)
y = a;
event
else
y = b;
end
always @ (posedge clk)
// procedural statements
list
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module design;
wire nsela;
wire nsel
wire selb
= !sel;
= sel & b;
Procedure
Procedure
// continuous statements
endmodule
Procedure
Procedure
if Statement Example
if is a conditional
statement
Each if condition is
tested in sequence
-Condition is boolean
expression
The first valid test
executes that branch
Conditions can overlap
Synthesis
if synthesis to mux structures
c
b
a
0101 d
0000
<=
=
0
0
y
1
1
mux
mux
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if Statement Syntax
if (CONDITION) begin
/ / procedural statements
end
if (CONDITION) begin
/ / procedural statements
end
else begin
/ / procedural statements
end
if (CONDITION) begin
/ / procedural statements
end
else if (CONDITION) begin
/ / procedural statements
end
else begin
/ / procedural statements
end
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for Loop
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a[0]
a[1]
a[2]
a[3]
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Synthesis
-for loop synthesizable for fixed range.
- repeat synthesizable for fixed repetitions
- while generally not synthesizable
- forever generally not synthesisable
repeat (expression)
begin
/ / statements
end
forever
begin
// statements
end
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Continuous Assignments
They are:
continuously driven
order independent
They:
operate on net data type only & reside outside
procedures
Example: wire a;
wire out;
..
assign a=x+y;
assign out=a+z;
x
y
z
a
+
out
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Multiple Continuous
Assignments
Example:
wire z;
.
..
assign z=a+b;
assign z=c+d;
a
b
c
d
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z
?
Multiple Continuous
Assignments
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Procedural Assignments
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Procedural Assignments
Example:
module andor(a,b,z_or,z_and);
input a,b;
output z_or,z_and;
reg z_or,z_and;
always @(a or b)
begin
if(a | b)
z_or=1;
else
procedural assignments
z_and=0;
if(a & b)
z_and=1;
else
z_and=0;
end
endmodule
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Example..
Code the following block:
a
b
sel
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Example..
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Conditional Assignments
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Conditional Assignment..
always @(a or b or c or sel)
z=(sel==0) ? a:((sel<=4b1010) ?b:c);
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Review
1.What
1
0
d[4:0]
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Contents
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2.
always @(posedge clk)
if(clr)
q <= 0;
else
q <= d;
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Example
Will this segment of code Swap the
upper and lower byte contents?
..
initial
begin
byte=8b00001111;
#20;
byte[3:0]=byte[7:4];
byte[7:4]=byte[3:0];
#20;
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Contents
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Non-Blocking Assignment
Non-blocking assignment:<=
Variable update is scheduled
-value is calculated and stored
-Variable is updated at the end of time slice
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Example
Yes !!!
Contents
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Simulation cycle(1)
___
___
Variable
Event list
a<=1
___
___
procedure
schedule
module sim_ex(a,m,y,w);
Input a;
Output m,y,w;
Reg m,y,w;
Always@ (a or m)
begin:p1
m<=a;
y<=m;
End
start
Always@ ( m)
begin:p2
w<=m;
End
endmodule
variable at
a:m:y:w=0
Simulation cycle(2)
___
___
____
Variable
Event list
m<=1
____
procedure
schedule
p1
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module sim_ex(a,m,y,w);
Input a;
Output m,y,w;
Reg m,y,w;
always@ (a or m)
begin:p1
m<=a;
y<=m;
End
Always@ ( m)
begin:p2
w<=m;
End
endmodule
variable at start
a:1,m:y:w:0
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Simulation cycle(3)
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module sim_ex(a,m,y,w);
Input a;
Output m,y,w;
Reg m,y,w;
____
____
Variable
Event list
m<=1 p1
_____
_____
procedure
schedule
always@ (a or m)
begin:p1
m<=a;
y<=m;
End
always@ ( m)
begin:p2
w<=m;
End
endmodule
variable at start
a:1,m:1y:w:0
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Simulation cycle(4)
____
____
Variable
Event list
y<=1
____
____
procedure
schedule
module sim_ex(a,m,y,w);
input a;
output m,y,w;
Reg m,y,w;
always@ (a or m)
begin:p1
m<=a;
y<=m;
end
always@ ( m)
W<=1
Procedure p1 and p2 execute(random)
Update to y and w scheduled
No change in value for m
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variable values
after one delta
a:1,m:1y:w:0
begin:p2
w<=m;
end
endmodule
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Simulation cycle(5)
____
____
Variable
Event list
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module sim_ex(a,m,y,w);
Input a;
Output m,y,w;
Reg m,y,w;
____
____
procedure
schedule
always@ (a or m)
begin:p1
m<=a;
y<=m;
End
always@ ( m)
variable
values after
two deltas
a:1,m:1y:1w:1
begin:p2
w<=m;
End
endmodule
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Simulation cycle:summary
Variable
Event list
a<=1
procedure
schedule
p1
m<=1
p1
p2
Y<=1
W<=1
variable
values
a:1,m:0
y:0,w:0
a:1,m:1
y:0,w:0
a:1,m:1
y:1,w:1
module sim_ex(a,m,y,w);
Input a;
Output m,y,w;
Reg m,y,w;
always@ (a or m)
begin:p1
m<=a;
y<=m;
End
always@ ( m)
begin:p2
w<=m;
End
endmodule
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Simulation time
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contents
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Non-blocking assignment
review
Non-blocking assignment:<=
Variable update is scheduled
-after the procedure suspends
..
reg q;
always @(posedge clk)
q<=d;
..
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contents
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initial
begin
avar=1b1;
bvar=1b1;
end
always @(posedge clk)
bvar<=avar+1b1;
always @(posedge clk)
cvar<=bvar;
Use non-blocking
assignment for
synchronous logic
begin
b=a;
c=b;
d=c;
end
Using blocking signal assignment
in clocked procedures can also
result in position dependent
code
begin
d=c;
c=b;
b=a;
end
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contents
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Combinational logic
always @ (a or b)
begin
m=a;
n=b;
p=m+n;
end
Use blocking assignment for combinational
procedures
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Combinational logic
always @(a or b or m or n)
begin:p1
m<=a;
n<=b;
p<=m+n;
end
Variable event
event list
a<=1
b<=2
m<=1
n<=2
p<=3
procedure
scheduler
p1
p1
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Multiple assignments
always @(a or b or c)
begin
m=a;
n=b;
p=m+n;
m=c;
q=m+n;
end
Multiple assignments should be either
blocking or non-blocking
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always @(a or b or c or m or n)
begin
m<=a;
n<=b;
p<=m+n;
m<=c;
q<=m+n;
end
Multiple assignments can be made to
a variable within one procedure
-last assignment wins for nonblocking
contents
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Mixed assignments
always @(posedge clk)
begin
tempa=ip1;
tempb=f(tempa);
op1<= tempb;
end
begin
temp=a+b;
q<=temp+c;
end
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Mixed assignments
Blocking assignments can be used within clocked
procedures for temporary variables
usage:
- assign inputs to temporary variables with blocking
assignment
-perform algorithm with temporary variables and
blocking assignment
-assign temporary variables to outputs with nonblocking assignment
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Topics
-Combinational Procedures
-Clocked procedures
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RTL Style
Combinational Procedure
always @ (a or b or c)
begin
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Clocked Procedure
always @ (posedge clock)
Begin
...
end
...
...
end
Tip
Tip
blocking assignment
Non-blocking assignment
(<=) should be used
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List for
combinational logic must
contain all variables read
within procedure
What would the behavior
be if sel was missing ?
always @ (a or b or sel)
begin
if (sel = = 1)
y = a;
else
y = b;
end
always @ (a or b)
a
b
always @ (a or b or sel)
begin
if (sel = = 1)
y = a;
else
y = b;
end
always @ (a or b or sel)
sel
sel
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Avoiding Latches
Two ways to
avoid latches:Use default
statement
Add else
clause
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always @ (ctrl or a)
begin
b = 0; // default
module complete2 (ctrl, a, b);
if (ctrl)
input a, ctrl;
b = a;
output b;
end
reg
b;
endmodule
always @ (ctrl or a)
begin
if (ctrl)
Question
b = a;
which do you think would be best for
else
a procedure with complex nested if
b = 0; / / default
end
statements?
endmodule
Continuous Assignments
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out
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count
0
+
<
0
1
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clock edge
Use only posedge/negedge in
event list
Registers are inferred on all
non-blocking assignments in
synchronous procedures
clk;
[3:0] count;
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sel
clk
Question
What is the issue with
this counter description?
Asynchronous Reset
endmodule
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always procedure
Event list only contains: posedge/negedge reset
posedge/negedge reset
for asynchronous reset
Code must follow these
templates
TIP
Keep procedures with asynchronous resets
separate from procedures with
synchronous resets.
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d
en
clk
0
1
mux
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clk
Question
How would you code this design in Verilog?
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* AIMS
- To introduce synthesis process and look at its strenths
and weaknesses
* TOPICS
- How a synthesis tool works
- Synthesis based methodology
- Synthesis strengths and weakness
- Programmable Logic device synthesis issues
- Language subsets
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clk
Synthesis
Engine
I/Speed
Constraints
File
Technology
library
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is the
* Verilog
important input - the
quality of results
depends
mainly on the code
* Technology Library
is used to build the
circuit from the verilog
description
* Constraints File
drives the synthesis
engine
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area/Speed Curve
Schematic
Gate Level Netlist
Area
Verilog
Constrains file
Boolean
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code
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Parsing
Mapping
Technology
Library
Gates
Optimization
Schematic
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clk
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? Question
What would be the input at ?
011
=
?
1 mux
b
a
clk
>
0
1mux
011
d
<
0
1 mux
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* Clock trees
- Usually require detailed, accurate net delay information
* Complex clocking schemes
- Synthesis tools prefer simple single clock
synchronous designs
* Memmory, IO pads, technology -specific cells
- You will probably need to instantiate these by hand
* Specific macro -cells
* Always as well as you can
- Although it can analyze hundreds of implementations
in the time taken for designer to analyze one
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A Synthesis Methodology
change code
tech library
synthesis
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netlist
n
y
meets area/speed?
verilog
rtl
simulation
testbench
change code
functional?
y
n
gate
simulation
compare
golden results
results
Language Support
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Synthesis Subset
Tool1
Tool2
Tool3
Tool4
Tool5
Summary
* RTL for synthesis
* Logic and gate optimization
* Coding style affects results
* Synthesis tools support subsets of
language style
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Guidelines
Use blocking assignments in always blocks that are
written to generate combinational logic
Use nonblocking assignments in always blocks that
are written to generate sequential logic
Comparison
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Coding Guidelines
Guideline 1
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temp
out
b
c
always
@(a or b or c)
temp = a & b;
out = c & temp;
endmodule
Guideline 2
In order to model sequential logic, use
non-blocking assignment statements
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Guideline 3
In order to model latches, use nonblocking statements
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Sensitivity List
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always
@(a or b or c)
temp = a & b;
out = c & temp;
endmodule
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output1
output2
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If/Case construct in
Combinational always block
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Correct implementation
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a
b
sig1
sig2
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wire nextZ;
assign nextZ = (a ^ b) & (sig1 | sig2);
always @(posedge CLK)
begin Q <= `TICK D;
Z <= `TICK nextZ;
end
a
b
sig1
sig2
Q
Z
nextz
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Indentation
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`define statements
Do not use hardwired constants all over the place;
instead, use meaningful names.
if (opcode == 6b`000010)
then begin
end else
if (opcode = 6b`000011)
then begin
end
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Priority Encoder
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Multiplexer
c
d
e
f
s
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Multiplexer vs Latch
a
y
b
a
select
if (select)
y = a;
else
y = b;
y
if (select)
y = a;
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data
clk
reset
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clk
en
clr
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Resource Sharing:I
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A
+
B
Mux
C
sum
if (select)
sum <= A + B;
else
sum <= C + D;
select
Resource Sharing:II
A
mux
B
select
C
mux
sum
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if (select) begin
temp1 <=
temp2 <=
end
else begin
temp1 <=
temp2 <=
end
sum <= temp1 +
select
A;
B;
C;
D;
temp2
Resource Sharing:III
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vsum
+
mux
Offset[0]
mux
mux
Offset[1]
0
Offset[2]
vsum = sum;
for (i=0;i<3;i++)
begin
if (req[i]=1b1) begin
vsum <= vsum + offset[i];
end;
end loop;
Resource Sharing:IV
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mux
vsum
R
+
0
Offset[0]
Offset[1]
mux
Offset[2]
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sum := start;
for (i=0;i<2;i++)
begin
sum <= sum + inc[i];
end;
start
inc[0]
+
+
inc[1]
+
inc[2]
sum
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Performance-oriented coding
start
inc[0]
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+
+
inc[1]
sum
+
inc[2]
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data_out
always @ (posedge clk) begin
if (req == 4'b1000)
data_out <= data_in;
end
end
clk
en
req
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data_out
clk
en
req[3]
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8-to-1 mux
DFF
r[4]
b[3:0]
r[0]
clk
r [3:1]
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Summary
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Topics
FSM Basics
Steps for FSM design
Example design
HDL code for FSM
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D
CLK
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Complex trasitions
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Possible
Possible
Possible
00p
Possible
Possible
Possible
25p
Possible
Possible
50p
FROM
Possible
75p
100p
What is an FSM?
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What is an FSM?
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FSM Structure
CONTROL
INPUTS
ASYNC
CONTROL
PORTS
NEXT
STATE
CURRENT
STATE
STATE
REGISTER
FLIP-FLOPS
REGISTERED
ACTION PORTS
CLOCK
COMB.
LOGIC
for
NEXT
STATE
COMBINATORIAL
ACTION PORTS
CURRENT
STATE
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01 =1b0
02 =1b0
3b000
a= 1b1
b=1 b 1
B
3b001
01 = 1b1
02 = 1b1
3b011
b= 1b o
{a, b} = 2b11
a= 1b0
{a ,b}=2b01
a =1b1
3b010
01 = 1b0
02 = 1b0
3b110
01= 1b0
02= 1b1
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State Names
(A,B,C,D,E,)
State encoding:
A=3 b000,
B=3b001
Transition
Conditions:
{a ,b}=2b01
Output values:
01=1b0
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begin: OUTPUTDECODE
// DEFAULT ASSIGNMENTS
01 = 1b0 ;
02 = 1b0 ;
case (state)
B: begin
01 = 1b1;
02 = 1b1;
end
E: 02 = 1b1;
end
end // end output decode logic
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If Synthesis
module if_example (a, b, c, ctrl,
op);
input
a, b, c;
input [3:0] ctrl ;
output
op;
reg
op;
always @ (a or b or c or ctrl)
if (ctrl) = = 4b0000)
op = a;
else if (ctrl < = 4b0100)
op = b ;
else
op = c ;
endmodule
Question
Draw the architecture of
hardware that this
represents.
<=
4
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op = a;
op = b;
op = c;
Question
What hardware structure is created
for a case statement?
ctrl
=
case (ctrl)
0:
0,1,2,3,4 :
default:
endcase
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ni
1
op
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Case
Synthesis
Case statement allowed to have overlapping choices
Choices prioritized in order of appearance
op = a ;
op = b ;
op = c ;
case (ctrl)
0:
op = a ;
1, 2, 3, 4 : op = b ;
default : op = c ;
endcase
4
ctrl
=
0
1
op
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case (ctrl)
0:
op = a ;
1, 2, 3, 4 :
op = b ;
default :
op = c ;
endcase
case (ctrl)
// rtl_synthesis parallel_case
0:
op = a ;
1, 2, 3, 4 :
op = b ;
default
op = c ;
endcase
ctrl
5
ctrl
<
>
op
parallel case synthesis
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Synthesis Directives
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case (test)
// rtl_synthesis parallel_case
2b00:
op = 1 ;
2b01,
2b10:
op = 2 ;
2b11:
op = 3 ;
default : // rtl_synthesis off
$ display (unknown test!);
// rtl_synthesis on
endcase
$display
writes a message
to the simulator
transcript window
Caution
Can lead to different
RTL/Gate level
functionality from
Same design use
With caution!
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Casez Synthesis
casez is treated similar to
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always @ (pri_in)
begin
casez (pri_in)
4 b1??? : op = 3 ;
4 b01?? : op = 2 ;
4 b001? : op = 1 ;
4 b0001 : op = 0 ;
default : op = 0 ;
endcase
end
always @ (ctrl)
begin
{int0, int1, int2 } = 3 b000
casez (ctrl)
3 b?/1 : int0 = 1 b1 ;
3 b?1?: int1 = 1 b1 ;
3b1?? : int2 = 1 b1 ;
endcase
end
Important
Make sure casez actually is parallel
before using directives
Question
Are these casez statements parallel
or not?
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always @ (ctrl or b or c)
case (ctrl)
0, 1:
op = b ;
2:
op = c ;
default : op = 0 ;
endcase
Caution
Make sure case actually is full
before using directives
always @ (ctrl or b or c)
begin
op = c ;
case (ctrl)
0, 1 : op = b ;
2 : op = c ;
endcase
end
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Question
There is latch inferred from
this code. What is the name
of the latches variable and
how can it be prevented?
Initial Statements
module counter (clk,
q);
input
clk ;
output [ 3 : 0 ] q ;
reg
[3:0] q:
initial q = 0 ;
always @ (posedge clk)
if (q > = 9)
q < = 4 b0 ;
else
q <= q+1;
endmodule
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Question
Synthesis
What does this initial statement mean: Synthesizable equivalent-add
1.For simulation?
reset
2.For synthesis?
Summary
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Structural Modeling
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* Aims
- Learn about the full capabilities of verilog for structural
,gate level modeling and modeling memories
* Topics
- Built in primitives
- Modeling memories
Structural Modeling
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out
nsel
selb
Conditional Primitives
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Functionality
Conditional buffer with logic 1 as enabling input
Conditional buffer with logic 0 as enabling input
Conditional inverter with logic 1 as enabling input
Conditional inverter with logic 0 as enabling input
Conditional Buffers
bufif1
data
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bufif1
out
enable
bufif1(out, data, enable)
enable
bufif1 0
1
x
0
z
0
L
z
1
H
data 1
x
z
x
x
z
z
x
x
out
data
enable
z
L
H
x
x
z
L
H
x
x
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my_rom_data
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0000
0101
1100
0011
1101
0010
0011
1111
1000
1001
1000
0001
1101
1010
0001
1101
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output word
address bus
memory
declaration
continuous
assignment
to output
Loading a Memory
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b1
bus_a
bus_b
b2
en_b_a
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bus_b
b2
en_b_a
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RAM cell
Test Bench
rd
data
bus
wr
module ram_cell (databus, rd, wr);
input databus;
input rd, wr;
reg datareg;
assign databus = rd ? datareg : bz;
always @ (negedge wr);
datareg <= databus;
endmodule
data
reg
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n1
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1
Lump the entire delay
at the last gate
net1
o1
out
3
2
distribute the
delay across each
gate
Typical delay specification Delays can be modeled in three ways :
delay from a to out =2
delay from b to out = 3
delay from c to out = 1
Lumped Delay
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#3
Distributed Delays
* distributed delays divide delay over more than one gate
- Allows different delays for different paths
- Delays accumulate along the path
a
b
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#2
#1
timescale 1ns / 1ns
module noror (out, a, b,
c);
output out;
input a, b, c;
nor #2 n1 (net1, a, b);
or #1 o1 (out, c, net1);
endmodule
n1
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net1
o1
path delays
a -> out is 2
out b -> out is 3
c -> out is 1
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* Specparam declares
parameters for specify block
* Must be declared inside
specify block
- Only visible inside block
* Cannot be over-ridden like
parameters
* Parameters cannot be used
inside a specify block
- Must use specparam
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*Rise, fall and turn-off delays can be specified for gates and module paths
- Rise is transition to 1
- Fall is transition to 0
- Turn-off is transition to z
and # (2, 3) (out, in1, in2, in3); // rise, fall
bufif0 #(3, 3, 7) (out, in, ctrl); // rise, fall. turn-off
spacify
(in => out) = (1, 2);
// rise, fall
(a = > b) = (5, 4, 7);
// rise, fall, turn-offs
endspecify
* Minimum , typical and maximum values can be specified for each delay
- Syntax - (minimum : typical : maximum)
or # (3 . 2 : 4 . 0 : 6 . 3) o1 (out, in1, in2); // min : typ : max
not # (1 : 2 : 3, 2 : 3 : 5) (o, in);
// min : typ : max for rise, fall
specify
// min:typ:max for rise, fall and turn-off
(b => y) = (2 : 3 : 4, 3 : 4 : 6, 4 : 5 : 8);
endspecify
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a
b
op
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Aims
* Learn how to build logic using user defined primitives
Topics
* Understand verilog composite libraries
* Understand functional modeling of ASIC libraries
* Learn about the use of UDPs in ASIC library models
WHAT IS A UDP ?
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Verilog has over two dozen gate level primitives for modeling
structural logic . In addition to these primitives Verilog has
user defined primitives (UDPs) that extend the built in
primitives by allowing you to define logic in tabular format.
UDPs are useful for ASIC library cell design as well as small
scale chip and medium scale chip design
* You can use UDPs to augment the set of predefined
primitive element s
* UDPs are self contained , they do not instantiate other
modules
* UDPs can represent sequential as well as combinational
elements
* UDP behavior is described in a truth table
* To use a UDP you instantiate like a built in primitive
FEATURES
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G4
G3
Cin
A
B
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Sum
G2
G1
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G5
Cout
U_ADDR2_S
Sum
U_ADDR2_C
Cout
You can implement the full adder with only two combinational UDPs
cont........next...
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ci
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
:
s
0;
1;
1;
0;
1;
0;
0
1
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Verilog has symbols that can be used in UDP table to improve readability
Symbol
Interpretation
Explanation
0 or 1
( 01)
0 -> transition
( 10 )
1 -> 0 transition
SUMMARY
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* UDPs allow you to create your own primitives to extend those built in
to Verilog
- Behavior is defined using a table
- UDPs are instantiated like built - in primitive
* They are a compact, efficient method of describing logic functions
- Both combinational and sequential behavior can be described
- UDPs are self - contained
- Many built - in primitives can be replaced by a single UDP
* There are some restrictions on using UDPs, including :- There must be a separate UDP for every output
- The Z value is not supported hence UDP ports can not be
bi - directional
- UDPs are not synthesisable
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Verification Overview
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Objectives
After completing this module ,you will be able to..
Understand verification flow
Testbench structure
Different ways of generating vectors
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Outline
Introduction
Vector generation
Simulation tips
summary
Verification Flow
System Specifications
TB
RTL
Test Pass
Yes
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Introduction
Purpose of writing testbench:
Instantiate the hardware model under test
Generate stimulus waveforms in the form of functional
test vectors during simulation
Generate expected waveforms in the form of reference
vector and compare with the output from RTL model
Pass or fail indication
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Introduction
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Testbench Structure
Vectors
Vectors
WAVE FORM
Test vectors
File
Reference Vectors
GENERATION
COMPARE
RESULTS
Results Files
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Outline
Introduction
Vector generation
Simulation tips
summary
Vector generation
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Vector generation
Different ways of generating system waveforms
a) Use continuous loops for repetitive signals
b) Use assignments for signals with few transitions
c) Use relative or absolute time generated signals
d) Use loop constructs for repetitive signal patterns
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Vector generation
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Outline
Introduction
Vector generation
Simulation tips
summary
Simulation tips
Simulate Corner Cases only
Use code coverage tools
Use the triple equals
Use the $display and $stop statements
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Summary
Verification flow
Testbenches
Simulation tips
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Verilog Testbenches
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Design Organization
include
files
design
files
file input:
stimulus
expects patterns
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vendor
libraries
simulator
compilation
simulation
data
clk
read
write
file output:
stimulus
results patterns
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initial
avec =
---------
compilation
procedure
procedure
procedure
initialization
procedure
x
procedure
procedure
l
procedure
simulation
procedure
Testbench
Testbench Organization
stimulus
Design
to verify
Testbench
stimulus
verify
results
Design
to verify
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* Simple testbench
- Just send data to desgin
- No interaction
- Few Processes
* Sophisticated testbench
- Models environment
around designs
- Talks to design
- Evolves towards
system model
- self - checking
In Line Stimulus
module inline_tb;
reg (7:0) data_bus, addr;
reg reset;
// instance of DUT
initial
begin
reset = 1bo;
data_bus = 8hoo;
# 5 reset = 1b1;
#15 reset = 1bo;
#10 data_bus = 8h45;
#15 addr = 8hf0;
#40 data_bus = 8h0f;
end
endmodule
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**Important
Do not forget to insert timin
control in the loop
Simple Delays
initial clk=0;
always clk = ~clk;
Will above code generate clk?
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Simple Delays
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Summary
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System Control
Objective:Describe some of the compiler directives ,
system tasks and system functions
available in Verilog
Topics:
Text output
Simulation control
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$display
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#10;
$display(At time %d in_bus is %h,$time,in_bus)
Output:
At time 10 in_bus is 1f
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$monitor
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-displays all values in the list each time any of them changes
-$monitor($time, " A = %b B = %b CIN = %b
SUM = %B CARRY = %b", A,B,CIN,SUM,CARRY);
$monitor
module TB_FULL_ADD;
reg A, B, CIN;
wire SUM, CARRY;
FULL_ADD U1(A, B, CIN, SUM, CARRY);
initial
begin
$monitor($time, " A = %b B = %b CIN = %b
SUM = %B CARRY = %b", A,B,CIN,SUM,CARRY);
A = 0; B = 0; CIN = 0;
#5 A =1;B = 0; CIN = 0;
#5 A =0;B = 1; CIN = 0;
#5 A =1;B = 1; CIN = 0;
#5 A =0;B = 0; CIN = 1;
#5 A =1;B = 0; CIN = 1;
#5 A =0;B = 1; CIN = 1;
#5 A =1;B = 1; CIN = 1;
#5 $finish;
end
endmodule
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$monitor
Monitor list for full adder test bench
0 a=0 b=0 CIN=0 SUM =0 CARRY=0
5 a=1 b=0 CIN=0 SUM =1 CARRY=0
10 a=0 b=1 CIN=0 SUM =1 CARRY=0
15 a=1 b=1 CIN=0 SUM =0 CARRY=1
20 a=0 b=0 CIN=1 SUM =1 CARRY=0
25 a=1 b=0 CIN=1 SUM =0 CARRY=1
30 a=0 b=1 CIN=1 SUM =0 CARRY=1
35 a=1 b=1 CIN=1 SUM =1 CARRY=1
$finish at simulation 40
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$monitor
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Simulation control
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simulation flow
#200 $stop;
simulation suspends
at time 200
#1000 $finish;
simulation terminates
at time 1000
Compiler directives
`include <file name>
Example:file global.txt
//clock and simulator constants
Parameter initial_clk=1;
Parameter period=20;
Parameter max_cycle=5;
Parameter end_time=period*max_ cycle
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Compiler directives:Example
Usage:
Module clock_gen;
`include global.txt
always
begin
$monitor( $time,\t clk=%d,clk);
clk=initial_clk;
while ($time<end_time)
begin
#(period/2)
clk=~clk ;
end
$display($time,simulation
ends)
$finish;
End
endmodule
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File outputs
32 channels available
32h000_0001
32h000_0800
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$fopen, $fclose
$fopen
integer chan_num1,chan_num2;
declaration of channel descriptors
Chan_num1=$fopen(file1.out);
Chan_num2=$fopen(file2.out);
Chan_num1=32h0000_0002(bit 1 set)
Chan_num2=32h0000_0004(bit 2 is set)
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init8X8.dat
@2
11111111
10101010
00000000
@6
Xxxxzzzz
1x1x1x1x
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mem8x8.out
memory[0]=xxxxxxxx
memory[1]=xxxxxxxx
memory[2]=11111111
memory[3]=10101010
memory[4]=00000000
memory[5]=xxxxxxxx
memory[6]=xxxxzzzz
memory[7]=1x1x1x1x
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(Task name)
input [7:0]in_bus;
output [3:0] count;
integer i;
begin
count=0;
#5;
for (i=0;i<8;i=i+1)
if(!in_bus[i])
count=count+1;
end
endtask
//assign outputs
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initial begin
clk=1;
p=0;
end
always #50 clk=~clk;
initial
begin
neg_edge(4);
p=1;
end
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endmodule
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module test_busif;
reg clk;
//clock generation
.
//instantiation of task module
mytask m1 ( ) ;
//creating stimulus..
Initial
begin
m1.neg_clocks(6);
m1.cpu_driver(8h00);
end
endmodule
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Function Declaration
function integer zero_count;
input [7:0]in_bus;
integer i;
begin
zero_count=0;
for (i=0;i<8;i=i+1)
if(!in_bus[i])
zero_count=zero_count+1;
end
endfunction
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function Call
module zfunct (a_bus,b_bus,clk,azero,b_count);
input[7:0] a_bus,b_bus;
input clk;
output azero, b_count;
reg azero;
Wire[3:0] b_count;
//function declaration
assign b_count=zero_count(b_bus);
always @(posedge clk)
if(zero_count(a_bus)==320)
azero=1b1;
else
azero=1b0
endmodule
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Functions
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Examples
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Verilog PLI
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Outline
Introduction
PLI Interface
TF/ACC Routines
Creating PLI Applications
Summary
Introduction
Verilog Programming Language Interface is
one of the most powerful features of Verilog
PLI provides both H/S designers to interface their
programs to commercial Verilog simulators
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Introduction
Generations of PLI
IEEE 1364 Verilog
TF / ACC routines.
PLI 1.0
1990
VPI routines
PLI 2.0
1993
Introduction
Capabilities of Verilog PLI
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Outline
Introduction
PLI Interface
TF/ACC Routines
Creating PLI Applications
Summary
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PLI Interface
User Design Representation
Invokes UserDefined
System
Task
And Stimulus
Pass
data
Internal design
Representation
(Data Structures)
Access
Internal
structures
PLI Library
Routines
Verilog Compilation
User Defined
System Task
#1
User-Defined
System Task #2
User-Defined
System Task #3
Invokes
UserPLI Library
defined C
Routines
routine
User-Defined
C routine # 1
User-Defined
C routine # 2
User-Defined
C routine #3
Simulation
Simulation Output
PLI Library
Routines to do
Miscellaneous
Operations
Objects in Verilog
Top-level modules
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Example
Example: 2-to-1 Multiplexer
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Outline
Introduction
PLI Interface
TF/ACC Routines
Creating PLI Applications
Summary
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TF/ACC Routines
Role of Access and Utility
Routine
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Outline
Introduction
PLI Interface
TF/ACC Routines
Creating PLI Applications
Summary
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Step I
module test;
reg a, b, ci;
wire sum, co;
...
initial
begin
...
$show_value (sum);
end
endmodule
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Step II
Two user-defined C routines will be associated with
$show_value:
A C routine to verify that $show_value has the correct
type of arguments
A C routine to print the name and logic value of the
signal
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/* calltf routine */
/* misctf routine */
/* system task/function name */
/* forward reference = true */
/* type of PLI routine */
/* user_data value */
/* checktf routine */
/* sizetf routine */
/* calltf routine */
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$show_value(sum);
$show_value(co);
$show_value(i1.n3);
#10 $stop;
$finish;
end
Endmodule
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Thank You
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Aims
To review basic Verilog concepts and code structures
To explore a real life example
Topics
FIFO Specification
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When write enable is high, data is written into FIFO and stored
When read enable is high, data is read from FIFO
In the same order that it was written
Both enable lines are not allowed to be active in the same clock
cycle
If this occurs, both read and write operations are suppressed
When the FIFO is full, set f_full high and ignore write operations
When the FIFO is empty, set f_empty high and ignore read
operations
FIFO should be parameterisable for data width and FIFO length
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FIFO Implementation
1
2 3 .
one
two
three
four
wr_ptr
n
FIFO
width
rd_ptr
rd_ptr
FIFO length
Read pointer
follows write
and accesses
data in same
order as
written
wr_ptr
write here
<free>
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wr_ptr
FIFO write:
assign data to
current write
pointer &
increment
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Design Constants
Parameters used to
define data and
0
address width
1
Must be declared
2
before input/output
.
.
ports
Values can be changed WIDTH-1
in module instantiation
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0 1 2
. .
. LENGTH-1
rd_ptr[ADDRESS_WIDTH-1 : 0]
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FIFO I/O
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// output declarations
output f_full;
output f_empty;
output [WIDTH-1:0] data_out;
data_in
WIDTH
fifo
WIDTH
wr_en
f_full
rd_en
f_empty
reset
// register declarations
// internal variable declarations
// functional code
endmodule
data_out
clock
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rd_ptr
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fiforeg
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
LENGTH-1.
[WIDTH 1 :0]
// functional code.
endmodule
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read operation:
increment read pointer
write operation: write
data at current pointer
and update pointer
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FIFO Outputs
Module fifo
/ / declarations
/ / clocked procedure
/ / full and empty pointers
assign and empty pointers
assign f_full = ( ( rd_ptr wr_ptr) = = 5b000001);
assign data_out= fiforeg[rd_ptr];
End module
Outputs are
combinational
If read pointer
catchers write
pointer, FIFO empty
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Testbench
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DUT Instantiation
module fifo_tb;
/ / Data type declaration
/ / FIFO instantiation
fifo # (WIDTH,
ADDRESS_WIDTH) dut (
.data_in (data_in)
.data_out (data_out),
.clock
(clock)
.reset
(reset)
.wr_en
(rd_en)
.f_full
(f_full),
.f_empty (f_empty)
/ / Apply stimuls
endmodule
Question
Why are there no ports for the test
fixture ?
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Testbench Declarations
module fifo_tb
Parameter WIDTH =8;
Parameter ADDRESS_WIDTH = 5:
Parameter PERIOD = 10;
/ / input declarations
reg [WIDTH-1:0] data;
reg clock, wr_en, rd_en, reset;
/ / output declarations
wire f_full;
Wire f_empty;
wire
endmodule
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Describing Stimulus
initial
begain
reset=1b0;
#2;
reset = 1b1;
#5;
reset =1b0;
@(negedge clock) ;
rd_en = 1b0;
wr_en = 1b1;
for (i = 0, i <35; i = i + 1)
begin
@(negedge clock);
data = 255 i;
end
halt simulation
Describing Stimulus
rd_en = 1b1;
wr_en = 1b0;
repeat (2)
@(negedge clock);
$stop;
end
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Review
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