DEVELOPMENT OF A DERIVATIVE

STANDARD CELL LIBRARY

BNM_LVT_45NM FOR CMOS
GPDK045 LIBRARY

- AJAY.G

Agenda
INTRODUCTION
PROBLEM DEFINITION & JUSTIFICATION
DELIVERABLES
BNM_LVT_45NM LIBRARY

DESIGN FLOW
DESIGN GUIDELINES
BNM_LVT_45NM DESIGN
DESIGN CHARACTERIZATION

RESULTS AND DISCUSSION

SCHEMATIC VIEW
LAYOUT VIEW
ABSTRACT VIEW
CHARACTERIZATION DATA
LEF
DEF

CONCLUSION
FUTURE SCOPE
PAPER PUBLICATIONS

Introduction
Standard cell based design is the most
practiced approach to implement an IC
This design flow requires a set of logic cells
whose characteristic behavior is well known
Such a set of logic cells is collectively called
as a Standard Cell Library.
Constituents of CMOS Standard Cell Library

Introduction contd.
The

components of a standard cell library are

Logical cells
Buffer Cells
Special Cells

Academic Cell libraries

S.I No.,

Library name

VTVT

OSU

NCSU

MSU

gpdk045

University /
Organisation
Virginia tech
Oklahoma state
university
North Carolina
State University
Mississippi State
university
Cadence

Technology
250nm & 180nm
250nm &180 nm

250 nm

180nm
45nm

Deliverables of
BNM_LVT_45nm
The

BNM_LVT_45nm library contains the

following deliverables
.lib (Liberty library file)
.LEF(Library exchange format)
.spi (Spice netlist)
Schematic representation
Layout View
Abstract view
Av_extracted view

Components of
BNM_LVT_45nm library
Cell Name

No., of Inputs

Drive strength

INVERTER

1X,2X,4X,16X,32X

BUFFER

1X,2X,4X,16X,32X

AND

2,3,4

1X,2X,4X

OR

2,3,4

1X,2X,4X

NAND

2,3,4

1X,2X,4X

NOR

2,3,4

1X,2X,4X

AOI

(21),(22),(211),(221),(222)

1X,2X,4X

OAI

(21),(22),(211),(221),(222)

1X,2X,4X

XOR

1X,2X

FULL ADDER

MUX

2X1,4X1

1X,2X

DFLIPFLOP

1X,2X

CLK GATE

1X

CLK BUFFER

1X

FILLER CELLS

BNM_LVT_45NM library
design

Standard Cell Library

Development- General
Flow
Schematic
Entry
Pre
Layout
Simulati
on
Library
Verification

Layout

Extraction

Post
Layout
Simulatio
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n

Abstract(LEF/
DEF)
Characteriz
ation
AJAY G 1BG10LVS01 BNMIT

Standard Cell
Library
9

EDA Tools
EDA Tool Name

Tool functionality

Cadence Virtuoso Schematic Editor XL

Schematic Entry

Cadence Virtuoso Analog Design Environment

Simulation Environment setup

Cadence Spectre Simulator

Spice Simulations /Functional Verification

Cadence Virtuoso Layout XL

Layout Entry

Cadence Assura DRC, LVS /

Design Rule Check and Layout vs. Schematic

Cadence Physical Verification

verification

Cadence QRC

Parasitic Extraction

Cadence Hierarchy Editor

Back annotation

Cadence Abstract Generator

Abstract View generation

Cadence LEF/DEF

LEF and DEF view generation

Cadence Encounter Library Characterizer

Characterization of Cells

Design Guidelines

Standard Cell design

template -Introduction
Cell height 3.36m
15 routing tracks

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AJAY G 1BG10LVS01 BNMIT

12

Pitch

Routing Grid
Horizontal

Vertical
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14

Routing Grid Definition

-Tracks
Horizontal

15 Routing Tracks

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Standard Cell Template

Vdd
Rail

PMOS
REGIO
N
Standar
d cell
height
Cell
Origin

NMOS
REGION

Vss Rail

Pin placement

Design

Design - Schematic Entry

Input file format

spice model files (.scs, .spi, .sp )

Output file format

Spice netlist (.scs, .spi, .sp )

Tool
Cadence Virtuoso Schematic

editor

Design Circuit Simulation

Tool
Spectre Simulator in Cadence Virtuoso ADE

Design- Layout

Input file format

Spice netlist (.scs, .spi, .sp )

Output file format

Intermediate layout data base

in .oa (Open Access)

Tool
Cadence Virtuoso Layout editor

Design - Parasitic Extraction

Input file format

Intermediate layout data base

in .oa (Open Access)

Output file format

Circuit Spice netlist (.scs, .spi,

.sp )

Tool
Cadence QRC extraction tool

Design- Post Layout Simulation

Physical

Simulation

Design- Abstraction
Abstract

View Generation

Cadence Abstract generator

Pin
Information

Design- Abstraction
LEF

file generation

The LEF file for all cells is generated using the

Cadence Virtuoso Toolset.

The LEF contains information about the physical
characteristics of the cells

Design Library
Characterization
.Lib

generation

Characterization of the BNM_LVT_45nm library cells is

carried out using Cadence Encounter Library

Characterizer
The Cadence Encounter Library Characterizer requires
the extracted spice netlists of BNM_LVT_45nm Cells.
The cells are characterized for different Process, voltage
and temperature conditions through spice simulations.
The characterization data is presented in a Liberty file
format (.Lib)

Design-Characterization
environment

Design - ELC Setup for

Characterization
The

ELC tool must be configured as per the

requirements of the characterization process

The
It

elccfg file is used to configure ELC.

contains information about model files,

spice subcircuit definitions, process for which

the cells must be characterized etc.

Design - Characterization
ELC

setup file

The ELC tool requires a setup file which contains

information about different process, voltage and

temperature conditions to be considered for
simulation.

Design Characterization -Process

conditions

Paramete
rs
Vdd
Ambient
Temperature

Process Corners
Min

Typical

MAX

0.9 V

1V

1.1 V

0C

25C

40C

RESULTS & DISCUSSIONS

Different

views of a cell in
BNM_LVT_45nm library
Schematic
Layout
Abstract
Spice netlist
Extracted view
LEF file
Liberty library file
DEF file

LEF- Library exchange

format

MACRO NOR2_X1
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN NOR2_X1 0 0 ;
SIZE 1.275 BY 3.36 ;
SYMMETRY X Y R90 ;
PIN y
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER Metal1 ;
RECT 1.025 1.02 1.16 1.08 ;
END
END y
PIN B
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER Metal1 ;
RECT 0.995 2.075 1.195 2.165 ;
END
END B

7/10/2011

PIN A
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER Metal1 ;
RECT 0.1 0.935 0.3 1.195 ;
END
END A
PIN gnd!
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER Metal1 ;
RECT 0.62 -0.06 0.68
0.025 ;
END
END gnd!
PIN vdd!
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER Metal1 ;
RECT 0.18 3.3 0.24 3.42 ;
END
END vdd!
OBS

AJAY G 1BG10LVS01 BNMIT

LAYER Metal1 ;
RECT 0 0 1.275
LAYER Metal2 ;
RECT 0 0 1.275
LAYER Metal3 ;
RECT 0 0 1.275
LAYER Metal4 ;
RECT 0 0 1.275
LAYER Metal5 ;
RECT 0 0 1.275
LAYER Metal6 ;
RECT 0 0 1.275
LAYER Metal7 ;
RECT 0 0 1.275
LAYER Metal8 ;
RECT 0 0 1.275
LAYER Metal9 ;
RECT 0 0 1.275
LAYER Metal10 ;
RECT 0 0 1.275
LAYER Metal11 ;
RECT 0 0 1.275
END
END NOR2_X1

3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;
3.36 ;

32

DEF- Design Exchange

format
VERSION 5.6 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;

DESIGN AND2_X1 ;

UNITS DISTANCE MICRONS 2000 ;

COMPONENTS 11 ;
- I__0 pmos1v_lvt_45 + PLACED ( 1370 3200 ) FN ;
- I__1 nmos1v_lvt_46 + PLACED ( 1250 1080 ) FN ;
- I__2 pmos1v_lvt_43 + PLACED ( 2550 2840 ) N ;
- I__3 nmos1v_lvt_47 + PLACED ( 810 1080 ) FN ;
- I__4 nmos1v_lvt_48 + PLACED ( 2250 670 ) N ;
- I__5 pmos1v_lvt_49 + PLACED ( 770 3200 ) N ;
- I__6 M1_PO_3 + PLACED ( 290 2220 ) N ;
- I__7 M1_PO_3 + PLACED ( 1610 2650 ) N ;
- I__8 M1_PO_3 + PLACED ( 2310 2080 ) N ;
- I__9 M1_NWELL_1 + PLACED ( 180 3230 ) N ;
- I__10 M1_PSUB_8 + PLACED ( 760 30 ) N ;
END COMPONENTS

END DESIGN

.LIB- Liberty library

format
Liberty

file for AOI211_X1

Cell Data Sheet

AOI211_X1:
Features:
Strength

1X

Cell Area

4.7376m2

Function

Y=!(((C1 & C2) | B) | A)

Type

Combinational

Input

A ,B ,C1,C2

Output

Power Supply

Vdd -1V, Gnd -0V

Cell Data Sheet Contd.

AOI211_X1
Propagation delay[ns]
0.0231

Input Transition[ns]

0.82

189.75

0.82

189.75

Fall

0.024328

0.585933

0.206251

1.14821

Rise

0.055338

1.87069

0.25112

2.2676

Fall

0.022713

0.556589

0.167128

1.11221

Rise
Fall
Rise
Fall
Rise

0.051787

1.86726

0.258417

2.33449

0.028018

1.12892

0.159901

1.62

0.036532

1.97481

0.213229

2.43432

0.030519

1.13184

0.165951

1.60209

0.042319

1.9964

0.249131

2.46087

Load Capacitance[fF]
A to Y
B to Y
C1 to Y
C2 to Y

1.2

Cell Data Sheet Contd.

Transition

Delay of AOI211_X1
Output Transition[ns]
0.0231

Input Transition[ns]

0.82

189.75

0.82

189.75

Fall

0.015902

0.803832

0.171114

0.846717

Rise

0.037977

2.438

0.148659

2.43649

Fall

0.013744

0.764636

0.170691

0.815712

Rise

0.038034

2.43745

0.175089

2.43724

Fall

0.020596

1.51654

0.181001

1.52304

Rise

0.036356

2.62274

0.191706

2.61927

Fall

0.020671

1.52994

0.162744

1.52109

Rise

0.041368

2.64366

0.191893

2.64294

Load Capacitance[fF]
A to Y

B to Y
C1 to Y
C2 to Y

1.2

Cell Data Sheet Contd.

Capacitance
Capacitance[fF]
A
B

Leakage
Power[nW]

1.09103

0.251096
1.15921

C1

0.931196

C2

0.11872

Power

Cell Data Sheet Contd.

AOI211_X1
Dynamic power consumption
Dynamic Power Consumption[nW]

0.0231

Input Transition[ns]

0.82

189.75

0.82

189.75

Fall

0.000471

0.076025

0.00102

0.07593

Rise

0.002707

0.079261

0.002881

0.079247

Fall
Rise
Fall
Rise
Fall

0.000273
0.002396
0.000188
0.001828
0.000174

0.076201
0.078959
0.076607
0.078421
0.076602

0.000873
0.002683
0.00041
0.002422
0.000207

0.076116
0.078947
0.07654
0.078469
0.076601

Load Capacitance[fF]

A to Y
B to Y
C 1to Y
C2 to Y

1.2

Conclusion - Highlights
Target

Library - 45nm technology

Standard cell height 3.36m (149)
Derivative library to gpdk045
It is a 15 track library
Supports core power supply 1V
Contains functional special cells filler cells
Liberty file format for all cells synthesis
LEF, DEF available for all cells
Cadence Design tools used for entire design flow
Low Vt transistors are used for all cells
Cells are operable upto 125 Celsius
Only Metal1,Metal2 and poly are used for intra-cell routing

Future Scope
The

Standard cell library is technology

dependent , hence as the technology shifts to
newer sub nano geometry nodes, a new cell
library must be developed.
Optimized versions of BNM_LVT_45nm
library can be developed focusing on either
low power or high performance cells.
It is also possible to scale down the library to
sub-45nm technology.

Publications
Title of the Paper
Accurate Power Measurement Methodology for VLSI Circuits Using CAD Tools
Name of the conference
International Conference on Devices ,Circuits and Systems
IEEE xplore paper ID

INSPEC Accession no: 12692787

ISBN no: 978-1-4577-1545-7

Venue
Karunya Univeristy, Coimbatore, India

References

Dimitris Bekiaris, Antonis Papanikolaou, Giorgos Stamelos, Dimitrios Soudris,

George Economakos and Kiamal Pekmestzi, A standard-cell library suite for
deep-deep submicron CMOS technologies, 6th International Conference on
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE
-2011 .

Jianping Hu and Jun Wang Low Leakage Power Designs of Basic Standard Cells
Using Gate-Length Biasing, IEEE 2011

Gerson Scartezzini, Ricardo Reis, Power Consumption in Transistor Networks

versus in Standard Cells, IEEE 2011.

Jeannette Donan Djigbenou, Thien Van Nguyen, Cheng Wei Ren, and Dong Sam
Ha, Development of TSMC 0.25m Standard Cell Library ,IEEE 2007

References- Contd.

Development and Distribution of TSMC 0.25 m Standard CMOS Library

Cells,Jeannette Donan Djigbenou and Dong Sam Ha,VTVT (Virginia Tech VLSI for
Telecommunications) Lab,IEEE 2007

Puneet Gupta, Andrew B. Kahng, Puneet Sharma, and Dennis Sylvester GateLength Biasing for Runtime-Leakage Control, IEEE 2006

Nguyen Minh Duc and Takayasu Sakurai Compact yet High-Performance (CyHP)
Library for Short Time-to-Market with New Technologies,ASP-DAC '00
Proceedings of the 2000 Asia and South Pacific Design Automation Conference,
2000

Asral bin Bahari Jambek, Ahmad Raif bin Mohd Noor Begand Mohd Rais Ahmad
Standard Cell Library Development, IEEE 1999

J.L. Noullet, A. Ferreira-Noullet Do We Need So Many Cells For Digital ASIC

Synthesis?, Institut National des Sciences Appliquees,Electron Technol (Warsaw).
Vol. 32, No. 3, Pp. 272-276. 1999 .

THANK YOU

Q&A