Introduction to FETs

Field-Effect Transistors

Introduction
An Overview of Field-Effect Transistors
Insulated-Gate Field-Effect Transistors
Junction-Gate Field-Effect Transistors
FET Characteristics
Summary of FET Characteristics
FET Amplifiers
Other FET Applications

Current Controlled vs Voltage Controlled Devices

The primary difference between the two types of

transistors is the fact that the BJT transistor is a
current-controlled device as depicted in , while the
JFET transistor is a voltage-controlled device as
shown in fig.
In other words, the current IC is a direct function of
the level of IB. For the FET the current I will be a
function of the voltage VGS applied to the input
circuit as shown in Fig.

 In each case the current of the output circuit is being

controlled by a parameter of the input circuitin one
case a current level and in the other an applied
voltage.
Just as there are npn and pnp bipolar transistors, there
are n-channel and p-channel field-effect transistors.
However BJT transistor is a bipolar devicethe prefix
bi- revealing that the conduction level is a function of
two charge carriers, electrons and holes. The FET is a
unipolar device depending solely on either electron (nchannel) or hole (p-channel) conduction.
In general, FETs are more temperature stable than BJTs, and FETs
are usually smaller in construction than BJTs, making them
particularly useful in integrated-circuit (IC) chips.

Introduction
Field-effect transistors (FETs) are probably the simplest form
of transistor
widely used in both analogue and digital applications
they are characterised by a very high input resistance and small physical
size, and they can be used to form circuits with a low power
consumption
they are widely used in very large-scale integration
two basic forms:
insulated gate FETs
junction gate FETs

Junction-Gate Field-Effect Transistors

Sometimes known as a JUGFET , another common name
the JFET
Here the insulated gate of a MOSFET is replaced with a
reverse-biased pn junction
Since the gate junction is always reverse-biased no current
flows into the gate and it acts as if it were insulated

Construction
two polarities: n-channel and p-channel

 Operation
the reverse-biased gate junction produced a depletion
layer in the region of the channel
the gate volt controls the thickness of the depletion
layer and hence the thickness of the channel
consider an n-channel device
the gate will always be negative with respect to the
source to keep the junction between the gate and the
channel reverse-biased
making the gate more negative increases the
thickness of the depletion layer, reducing the width
of the channel increasing the resistance of the
channel.

The effect of varying the gate voltage

JFET circuit symbols

FET Characteristics
Drain Characteristic Curve
VGS = 0 V
As VDD (and thus VDS) is increased
from 0 V, ID will increase
proportionally, as shown in the graph
of Figure between points A and B. In
this area, the channel resistance is
essentially constant because the
depletion region is not large enough
to have significant effect. This is
called the ohmic region because
VDS and ID are related by Ohms
law

 At point B in fig ,the curve levels off and enters the active
region where ID becomes essentially constant. As VDS
increases from point B to point C, the reverse-bias voltage
from gate to drain (VGD) produces a depletion region large
enough to offset the increase in VDS, thus keeping ID
relatively constant.

Pinch-Off Voltage:
The value of VDS at which ID becomes essentially constant
(point B on the curve in Fig) is the pinch-off voltage, VP.
For a given JFET, VP has a fixed value which is taken at Vgs
= 0 (gate is shorted to ground).
A continued increase in VDS above the pinchoff voltage
produces an almost constant drain current. This value of
drain current is IDSS (Drain to Source current with gate
Shorted) and is always specified on JFET datasheets.
IDSS is the maximum drain current that a specific JFET can
produce regardless of the external circuit, and it is always
specified for the condition, VGS =0 V.

Breakdown:
Breakdown occurs at point C when ID begins to increase very
rapidly with any further increase in VDS.

Breakdown can result in irreversible damage to the device, so

JFETs are always operated below breakdown and within the
active region (constant current) (between points B and C on the
graph).

VGS Controls ID:

VGS is set to increasingly more negative values by adjusting
VGG, a family of drain characteristic curves is produced, as
shown in Fig.
Notice that ID decreases as the magnitude of VGS is increased
to larger negative values because of the narrowing of the
channel.

 Also notice that, for each increase in VGS, the JFET

reaches pinch-off (where constant current begins) at values
of VDS less than VP. The term pinch-off is not the same as
pinchoff voltage, Vp. Therefore, the amount of drain
current is controlled by VGS.

 Cutoff Voltage:
The value of VGS that makes ID approximately zero is the
cutoff voltage, VGS(off), The JFET must be operated
between VGS 0 V and VGS(off).
For this range of gate-to-source voltages, ID will vary
from a maximum of IDSS to a minimum of almost zero.
Cutoff effect is caused by
the widening of the depletion
region to a point where it
completely closes the
channel, as shown in Fig.

Comparison of Pinch-Off Voltage and Cutoff Voltage:

VP and VGS(off) are always equal in magnitude but
opposite in sign. A datasheet usually will give either
VGS(off) or VP, but not both. However, when you know
one, you have the other.
For example, if VGS(off) = -5 V, then VP = +5 V, as shown
in drain Fig above.

JFET Universal Transfer Characteristic

As range of VGS values from zero to VGS(off) controls the amount of

drain current. For an n-channel JFET, VGS(off) is negative, and for a
p-channel JFET, VGS(off) is positive. Because VGS does control ID,
the relationship between these two quantities is very important.
Fig below is a general transfer characteristic curve that illustrates
graphically the relationship between VGS and ID. This curve is also
known as a transconductance curve.

The transfer characteristic curve can also be developed from the drain
characteristic curves by plotting values of ID for the values of VGS
taken from the family of drain curves at pinch-off, as illustrated in Fig
below. for a specific set of curves. Each point on the transfer
characteristic curve corresponds to specific values of VGS and ID on
the drain curves.

For the BJT transistor the output current IC and input controlling
current IB were related by beta,

In above Eq a linear relationship exists between IC and IB. Double the

level of IB and IC will increase by a factor of two also.
Unfortunately, this linear relationship does not exist between the
output and input quantities of a JFET. The relationship between ID and
VGS is defined by Shockleys equation

The squared term of the equation will result in a nonlinear relationship

between ID and VGS, producing a curve that grows exponentially with
decreasing magnitudes of VGS.

JFET Parameters
The important parameters of JFET are as follows:
1) Transconductance(gm)
2) Input resistance and capacitance
3) Drain to source resistance.(rd).

Transconductance
Transconductance is the property of certain electronic
components. Conductance is the reciprocal of resistance.
Transconductance is the ratio of the current variation at the
output to the voltage variation at the input. It is written as
gm. It is defined as follows:
As the term transistor is a contraction of transfer resistance.
It refers to the ratio between a change of the voltage at two
output points and a related change of current through two
input points, and is notated as rm:
Transconductance is a contraction of transfer conductance.

JFET Forward Transconductance

The forward transconductance (transfer conductance), gm, is the

change in drain current
for a given change in gate-to-source
voltage
with the drain-to-source voltage constant. It is
expressed as a ratio and has the SI unit of siemens, S(1 siemens = 1
ampere per volt).).

gm is an important factor in determining the voltage gain of a FET

amplifier. Because the transfer characteristic curve for a JFET is
nonlinear, gm varies in value depending on the location on the curve
as set by VGS.
The value for gm is greater near the top of the curve (near VGS =0)
than it is near the bottom (near VGS(off)), as illustrated in Fig

 A datasheet normally gives the

value of gm measured at
VGS=0V (gm0).Given gm0, you
can calculate an approximate
value for gm at any point on the
transfer characteristic curve
using the following formula:

When a value of gm0 is not available, you can calculate it using

values of IDSS and VGS(off ). The vertical lines indicate an absolute
value (no sign).

Input Resistance and Capacitance

As JFET operates with its gate-source junction reverse-biased, which
makes the input resistance at the gate very high.
JFET datasheets often specify the input resistance by giving a value
for the gate reverse current, IGSS, at a certain gate-to-source
voltage. The input resistance can then be determined using the
following equation.
The input capacitance, Ciss, is a result of the JFET operating with a
reverse-biased pn junction.
Reverse-biased pn junction acts as a capacitor whose capacitance
depends on the amount of reverse voltage.
For example, the 2N5457 has a maximum Ciss of 7 pF for VGS 0.

AC Drain-to-Source Resistance
As mention in the drain characteristic curve that, above
pinch-off, the drain current is relatively constant over a
range of drain-to-source voltages. Therefore, a large
change in VDS produces only a very small change in ID.
The ratio of these changes is the ac drain-to source
resistance of the device, rds.

Datasheets often specify this parameter in terms of the

output conductance, gos, or output admittance, yos, for
VGS=0V.

 Admittance:
Admittance Y is the reciprocal of impedance. It is also a
complex quantity: real part is called conductance ( C ) and
the imaginary part is called susceptance ( B ).
The unit of admittance is Siemens (S)
Y = G + jB
Where, Y is admittance; G represents conductance and B
susceptance.

JFET Biasing
Self Bias
Voltage Divider Bias
Current Source Bias

Self-Bias
As JFET must be operated such that the gate-source
junction is always reverse-biased.
This condition requires a negative VGS for an n-channel
JFET and a positive VGS for a p-channel JFET. This can
be achieved using the self-bias arrangements shown in Fig
below.
The gate resistor, RG, does not affect the bias because it
has essentially no voltage drop across it and therefore the
gate remains at 0 V. RG is necessary only to force the gate
to be at 0 V and to isolate an ac signal from ground in
amplifier applications .

 For the n-channel JFET in Fig (a),

For the p-channel JFET shown in Fig b

Example-8.6
Find VDS and VGS in Fig

Setting the Q-Point of a Self-Biased JFET

The basic approach to establishing a JFET bias point is to
determine ID for a desired value of VGS or vice versa.
Then calculate the required value of RS using the
following relationship.

For a desired value of VGS, ID can be determined in either

of two ways: from the transfer characteristic curve for the
particular JFET or from Equation

Example

Example

Midpoint Bias
It is usually desirable to bias a JFET near the midpoint of its transfer
characteristic curve where ID IDSS/2.
Under signal conditions, midpoint bias allows the maximum amount of drain
current swing between IDSS and 0.

To set the drain voltage at midpoint (VD=VDD/2), select a value of

RD to produce the desired voltage drop.
Choose RG arbitrarily large to prevent loading on the driving stage
in a cascaded amplifier arrangement.

Graphical Analysis of a Self-Biased JFET

We can use the transfer characteristic curve of a JFET and
certain parameters to determine the Q-point (ID and VGS) of
a self-biased circuit.

To determine the Q-point of the circuit in Fig (a), a self-bias

dc load line is established on the graph as follows.
.

 First, calculate VGS when ID is zero

This establishes a point at the origin on the graph (ID=0,

VGS=0).
Next, calculate VGS when ID=IDSS. From the curve in
Fig above, IDSS =10 mA.

This establishes a second point on the graph (ID = 10 mA,

VGS = -4.7 V).
Now, with two points, the load line can be drawn on the
transfer characteristic curve as shown in Fig below.


The point where the load line intersects the transfer
characteristic curve is the Q-point of the circuit as shown, where
ID = 5.07 mA and VGS = -2.3 V.

Voltage-Divider Bias
An n-channel JFET with voltage-divider bias is shown in Fig.
The voltage at the source of the JFET must be more positive than
the voltage at the gate in order to keep the gate-source junction
reverse-biased.

Graphical Analysis of a JFET with Voltage-Divider Bias

An approach similar to the one used for self-bias can be used with
voltage-divider bias to graphically determine the Q-point of a
circuit on the transfer characteristic curve.
In a JFET with voltage-divider bias when ID=0, VGS is not zero,
as in the self-biased case, because the voltage divider produces a
voltage at the gate independent of the drain current.
The voltage-divider dc load line is determined as follows.

Therefore, one point on the line is at ID = 0 and VGS = VG.

 A second point on the line is at ID=VG/RS and VGS=0. The generalized

dc load line is shown in Fig below. The point at which the load line
intersects the transfer characteristic curve is the Q-point.

Q-Point Stability
Unfortunately, the transfer characteristic of a JFET can differ
considerably from one device to another of the same type.
For example, a 2N5459 JFET is replaced in a given
bias circuit with another 2N5459, the transfer haracteristic curve can
vary greatly, asillustrated in Fig(a).
In this case, the maximum IDSS is 16 mA and the minimum IDSS is
4 mA. Likewise, the maximum VGS(off ) is -8 and the minimum
VGS(off ) is -2 This means that if you have a selection of 2N5459s
and you randomly pick one out, it can have values anywhere within
these ranges.
If a self-bias dc load line is drawn as illustrated in Fig(b), the same
circuit using a 2N5459 can have a Q-point anywhere along the line
from Q1, the minimum bias point, to Q2, the maximum bias point.
Accordingly, the drain current can be any value between ID1 and
ID2, as shown by the shaded area.

This means that the dc voltage at the drain can have a range of values
depending on ID. Also, the gate-to-source voltage can be any value
between VGS1 and VGS2, as indicated.

 Fig below illustrates Q-point stability for a self-biased JFET and for
a JFET with voltage divider bias.
With voltage-divider bias, the dependency of ID on the range of Qpoints is reduced because the slope of the load line is less than for
self-bias for a given JFET.
Although VGS varies quite a bit for both self-bias and voltagedivider bias, ID is much more stable with voltage-divider bias.

Current-Source Bias
Current-source bias is a method for increasing the Q-point
stability of a self-biased JFET by making the drain current
essentially independent of VGS. This is accomplished by using a
constant-current source in series with the JFET source, as shown
in Fig.
In this circuit, a BJT acts as the constant-current source because
its emitter current is essentially constant if
A FET
can also be used as a constant current source.

In fig below its shown that ID remains constant for any transfer
characteristic curve, as indicated by the horizontal load line ,

Ohmic Region
The ohmic region extends from the origin of the
characteristic curves to the break point of the VGS=0
curve in a roughly parabolic shape, as shown on a typical
set of curves in Fig below.
The characteristic curves in this region have a relatively
constant slope for small values of ID.
The slope of the characteristic curve in the ohmic region is
the dc drain-to-source conductance GDS of the JFET.

As resistance is the reciprocal of the conductance Thus, the

dc drain-to-source resistance is given by

 A JFET can be biased in either the active region or the ohmic

region.
JFETs are often biased in the ohmic region for use as a voltage
controlled variable resistor. The control voltage is VGS, and it
determines the resistance by varying the Q-point.
To bias a JFET in the ohmic region, the dc load line must
intersect the characteristic curve in the ohmic region, as
illustrated in Fig below .
To do this in a way that allows VGS to control RDS, the dc
saturation current is set for a value much less than IDSS so that
the load line intersects most of the characteristic curves in the
ohmic region, as illustrated. In this case,

 As you move along the load line in the ohmic region of Fig
above , the value of RDS varies as the Q-point falls
successively on curves with different slopes.
The Q-point is moved along the load line by varying
VGS= 0 to VGS = -2 V, in this case.
As this happens, the slope of each successive curve is less
than the previous one. A decrease in slope corresponds to
less ID and more VDS, which implies an increase in RDS.
This change in resistance can be exploited in a number of
applications where voltage control of a resistance is useful.

Q-point at the Origin

In certain amplifiers, we may want to change the resistance seen by
the ac signal without affecting the dc bias in order to control the gain.
Sometimes JFET is used as a variable resistance in a circuit where
both ID and VDS are set at 0,which means that the Q-point is at the
origin.
A Q-point at the origin is achieved by using a capacitor in the drain
circuit of the JFET.
This makes the dc quantities VDS=0 V and ID=0 mA, so the only
variables are VGS and Id, the ac drain current.
At the origin we have the ac drain current controlled by VGS.
As transconductance is defined as a change in drain current for a
given change in gate-to-source voltage. So, the key factor when we
bias at the origin is the transconductance.

 At the origin, where VDS =0 V and ID= 0 mA, the formula

for transconductance, introduced earlier in this chapter, is

where gm is transconductance and gm0 is transconductance

for VGS=0V. gm0 can be calculated
from the following equation, which was also given earlier: