SUMMER TRAINING

ON

VLSI DESIGN & EMBEDDED

SYSTEM(VDES-2015)
16 JUNE 15 JULY,2015

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
MOTILAL NEHRU NATIONAL INSTITUTE OF

Introduction
to
VERILOG HDL

What is HDL?
Hardware description language (HDL) is a

specialized computer language used to program

the structure, design and operation of electronic
circuits.
Designers can write RTL description without
choosing a specific technology.
With the advent of VLSI, it is not possible to
verify a complex design with millions of gates on
a breadboard, HDLs came into existence to verify
the functionality of these circuits.

Most Commonly used HDLs

Verilog
Verilog HDL is commonly used in the US industry.
Its used in the design, verification, and implementation
of digital logic chips .
VHDL
VHDL (VHSIC (Very High Speed Integrated Circuits)
hardware description language) is more popular in
Europe.
Commonly used as a design-entry language for fieldprogrammable gate arrays. Field-Programmable Gate
Array is a type of logic chip that can be programmed

Difference between Verilog and

VHDL
Verilog

VHDL

1.

Based on C

Based on Pascal and

Ada

2.

Case sensitive

Case insensitive

3.

Weak and Limited

Language

Strong and Rich

Language

4.

Predefined Datatypes
are available

Explicit Datatypes
Conversion is needed

HISTORY
1985: Verilog language and related simulator Verilog-XL were

developed by Gateway Automation.

1989: Cadence design system purchased Gateway Automation.
1990: Open Verilog international formed.
1995: IEEE standard 1364 adopted.
2001: Created better Verilog standard IEEE 1364.
Continued ..

Three factors to success of Verilog

Programming Language Interface (PLI)

Extend and customize simulation environment

Close attention to the needs of ASIC foundries

Gateway Design Automation partnership with

Motorola, National, and UTMC in 1987-89

Verilog-based synthesis technology

Gateway Design Automation licensed Verilog to

Cadence
Synopsys introduced synthesis from Verilog in 1987

Module Representation
Verilog provides the concept of module.
A module is a
Basic Building block in Verilog
It can be a single element or collection of lower design blocks
Syntax:
module <module-name>(inputs, outputs);
//Define inputs and outputs

endmodule

Input Output Definition

Once the module is defined at the start, the inputs and

outputs are to be defined explicitly.

Input a , b //means there are 2 inputs of one bit each
If input or output is more than 1 bit i.e. two or more bits,

then the definition will be:

input [3:0] A, B;

//4 bit input A3-A0

output [3:0] C;

//4 bit output C3-C0

Levels of Abstraction
There are Three different levels of abstraction in verilog:
Gate level
Data flow
Behavioral /Algorithmic

1. Gate Level Modeling

In gate level modeling a circuit can be defined by use of logic gates.
These gates predefined in verilog library.
The basic gates and their syntax is as follows:
not gate_name (output, input);
and gate_name(output, input);
or gate_name(output, input);
nand gate_name(output, input);
nor gate_name(output, input);
xor gate_name(output, input);
xnor gate_name(output, input);

2. Data Flow Modeling

Continuous assignment statement is used.
Keyword assign is used followed by =
assign y = ~ x ;
// Not
assign y = a & b;
// And
assign w = a ^ b;
// Ex-Or
assign x = a + b;
// Or
assign y = s ? b : a
// 21multiplexer
when s = 1 , y = b
when s = 0 , y = a

Design Block

GATE LEVEL
module practice (y, a, b); // module definition
input a, b;
// by default it takes 1 bit input
output y;
// one bit output
and gate_1(y, a, b) ;
endmodule

DATAFLOW LEVEL

module practice (y, a, b);

// module definition

input a, b;

// by default it takes 1 bit input

output y;

// one bit output

assign y = a & b;
endmodule

BEHAVIORAL LEVEL

module practice (y, a, b);

//module definition
input a, b;
// by default it takes 1 bit input
output y;
// one bit output
always @ (a,b)
begin
case ({a,b})
2b00: y=1b0;
2b01: y=1b0;
2b10: y=1b0;
2b11: y=1b1;
endcase
end
endmodule

To create a new project

FPGA SPARTAN 2 IC

To Create an HDL source

RTL SCHEMATIC

CREATING TEST BENCH

WAVEFORM

OUTPUT WAVEFORM

THANK YOU !