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N A 10 to 10 cm
15
16
(2)
The band-gap between the conduction band and the valence band for silicon is
approximately 1.1 eV.
The location of the equilibrium Fermi level E F within the band-gap is determined by the
doping type and the doping concentration in the silicon substrate.
The Fermi potential F , which is a function of temperature and doping, denotes the
Ei , and the Fermi levelEF
difference between the intrinsic Fermi level
(3)
(4)
(5)
The definitions given in (4) and (5) result in a positive Fermi potential for n-type
material, and a negative Fermi potential for p-type material
The electron affinity of silicon, which is the potential difference between the
q
conduction band level and the vacuum (free-space) level, is denoted by
The energy required for an electron to move from the Fermi level into
q S , and is given by
free space is called the work function
(6)
Energy band diagrams of the components that make up the MOS system
q M = Work Function of Metal
Accumulation
Depletion
Inversion
Accumulation
VG << VTN
Depletion
VG < VTN
Inversion
VG > VTN
Accumulation
If a negative voltageVG is applied to the gate electrode, the holes in the p-type
substrate are attracted to the semiconductor-oxide interface.
The majority carrier concentration near the surface becomes larger than the
equilibrium hole concentration in the substrate; hence, this condition is called
carrier accumulation on the surface.
Note that in this case, the oxide electric field is directed towards the gate
electrode.
The negative surface potential also causes the energy bands to bend upward
near the surface.
While the hole density near the surface increases as a result of the applied
negative gate bias, the electron (minority carrier) concentration decreases as
the negatively charged electrons are pushed deeper into the substrate.
The cross-sectional view and the energy band diagram of the MOS structure
operating in accumulation region
The cross-sectional view and the energy band diagram of the MOS structure
operating in depletion mode, under small gate bias
(10)
(11)
The depletion region charge density, which consists solely of fixed acceptor
ions in this region, is given by
(12)
The cross-sectional view and the energy band diagram of the MOS structure in
surface inversion, under larger gate bias voltage
Circuit symbols
Band diagram of the MOS structure underneath the gate, at surface inversion.
Notice the band bending by 2 F at the surface.
V1 GC
The externally applied gate voltage is required to achieve surface inversion
So the second component of the threshold voltage.
As S F
V2 S F 2F
V3
QB
Cox
Qox
V4
Cox
VT V1 V2 V3 V4
For zero substrate bias, the threshold voltage VT 0 is expressed as follows
Where
It is seen that the threshold voltage variation is about 1.3 V over this range,
which could present serious design problems if neglected.
So the substrate-bias effect is unavoidable in most digital circuits and that the
circuit designer usually must take appropriate measures to account for and/or
to compensate for the threshold voltage variations.
Assumption: The entire channel region between the source and the drain is
inverted, i.e.,
(15)
(17)
(18)
(19)
(20)
(21)
or
(22)
where the parameters k and k' are defined as
process transconductance parameter
gain factor
Current-voltage relationship is affected by to the process dependent constants
k' , VT0, and is also affected by the device dimensions, W and L.
which guarantee that the entire channel region between the source and the
drain is inverted.
This condition corresponds to the linear operating mode for the MOSFET
Hence, the current equation (20) is valid only for the linear mode operation.
VDS~ ID Curve
It is to be noted that the VDS measured relative to the source increases from 0
to VDS as we travel along the channel from source to drain. This is because the
voltage between the gate and points along the channel decreases from VGS at the
source end to VGS-VDS.
When VDS is increased to the value that reduces the voltage between the gate and
channel at the drain end to VT that is ,
VGS-VDS=VT
or
Definition
Condition for Saturation
When
(23)
This expression indicates that the saturation drain
current has no dependence on VDS
Note that at the edge of saturation, i.e., when the drain-to-source voltage
reaches VDSAT,
Consequently, the effective channel length (the length of the inversion layer
where GCA is still valid) is reduced to
The gradual channel approximation is valid in this region; thus, the channel
current can be written
(24)
Thus, (24) accounts for the actual shortening of the channel, also called
channel length modulation.
(25)
The first term of this saturation current expression accounts for the channel
modulation effect, while the rest of this expression is identical to (23).
Empirically
(26)