DESIGN & STUDY OF A LOW POWER HIGH

SPEED FULL ADDER USING GDI MULTIPLEXER

ADDERS
The simple addition consists of
0+0=0
0+1=1
1+0=1
1+1=10

The highest significant bit is known as carry.

The combinational circuit that performs addition of two bits is called Half adder.

The combinational circuit that performs addition of three bits is called Full adder.
 MULTIPLEXERS

A digital multiplexer (MUX) is a combinational circuits that

selects one input out of several inputs and direct it to a
single output.

The particular input selection is controlled by a set of select

inputs.

For selecting one out of n input, a set of m select inputs is

required where n = m times of 2
 DEMULTIPLEXER

A Demultiplexer is a circuit having opposite operation to

multiplexer.

A digital Demultiplexer (DEMUX) is a combinational

circuits that assigns input to one of the several
outputs.

The particular output line selection is controlled by a set

of select inputs.

For selecting one out of n output, a set of m select inputs

is required where n = m times of 2
 COMPLEMENTARY CMOS & GDI CELL

Complementary CMOS logic gates

nMOS pull-down network pMOS
pull-up
pMOS pull-up network network
a.k.a. static CMOS inputs
output

nMOS
pull-down
network

GDI (Gate Diffusion Input) - a new technique of

low power digital circuit design is described.
This technique allows reducing power
consumption, delay and area of digital circuits,
while maintaining low complexity of logic
Fig: GDI basic cell consisting
of pMOS and nMOS design.
 CONVENTIONAL 28-T CMOS 1 BIT FULL ADDER

In full adder the sum and carry

outputs are represented as the
following two combinational,
Boolean functions of the three
Input input variables A, B and
C.

1 Bit Full Adder CMOS logic

 ARCHITECTURE OF MUX USING GDI TECHNIQUE

The basic architecture of the 2:1 MUX

using GDI method is shown in fig.
In this configuration we have
connected PMOS and NMOS gate
along with a SEL line A, as in MUX.
As we know that PMOS works on
ACTIVE LOW and NMOS works on
ACTIVE HIGH. So, when the SELECT
input is low (0) then the PMOS get
activated, and show the input B in
the output and due to low input (0)
Fig. Basic view of 2T the NMOS stands idle, as it is
MUX using GDI activated in high input.
technique
GDI CELL BASED VARIOUS LOGIC FUNCTIONS USING
DIFFERENT
INPUT CONFIGURATIONS AND CORRESPONDING
TRANSISTOR COUNTS
LOW POWER FULL ADDER USING 2T MUX

Block Diagram of Low Power Proposed Full Adder using 2T MUX

1OT BASED GDI FULL ADDER
DSCH2 SOFTWARE
SCHEMATIC DESIGN

GENERATING VERILOG FILE.

 MICROWIND 2.0 SOFTWARE

Layout Design
Area Calculation.
 MICROWIND 2.0
Power calculation
CONCLUSION

Now we can conclude that our proposed full adder has got better performance
in delay, power and area consideration in comparison with conventional full adder.

It shows that in contrast to other conventional techniques, this approach is

better and it will be more appropriate for industrial practice in complex process
technologies.
 THANK
YOU