Recall Last Lecture

The MOSFET has only one current, I D

Operation of MOSFET
NMOS and PMOS
For NMOS,
VGS > VTN
VDS sat = VGS VTN

For PMOS
VSG > |VTP|
VSD sat = VSG + VTP

Electronics
 ID versus VDS (NMOS) or ID versus VSD
(PMOS)

Electronics
 NMOS PMOS
o VTN is POSITIVE o VTP is NEGATIVE
o VGS > VTN to o VSG > |VTP| to turn
turn on on
o Triode/non- o Triode/non-
saturation region saturation region

o Saturation region o Saturation region

o VDSsat = VGS - VTN o VSDsat = VSG + VTP

Electronics
 DC analysis of FET

Electronics
 MOSFET DC Circuit Analysis
- NMOS
The source terminal is
at ground and common
to both input and output
portions of the circuit.
The CC acts as an open
circuit to dc but it allows
the signal voltage to the
gate of the MOSFET.
In the DC equivalent circuit, the gate current into the transistor is
zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH = R2 VDD
R1 + R2
Use KVL at GS loop:
VGS VTH + 0 = 0
Electronics VGS = VTH
 MOSFET DC Circuit Analysis
- NMOS
1. Calculate the value of V GS

2. Assume the transistor is biased in the saturation

region, the drain current:

3. Use KVL at DS loop

IDRD + VDS VDD = 0

4. Calculate VDSsat = VGS - VTN

5. Confirm your assumption:

If VDS > VDS(sat) = VGS VTN, then the transistor is biased in the
saturation region. If VDS < VDS(sat), then the transistor is biased in the
Electronics non-saturation region.
 EXAMPLE:
Calculate the drain current and drain to source voltage of a common source
circuit with an n-channel enhancement mode MOSFET. Assume that R1 = 30
k, R2 = 20 k, RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2

VTH = 20 5 = 2V hence VGS = VTH = 2V

30 + 20

VDSsat = VGS VTN = 2 1 = 1V, so, VDS > VDSsat, our assumption
that the transistor is in saturation region is correct

Electronics
 EXAMPLE
VDD =
10V
The transistor has
parameters VTN = 2V and
R1 = RD =
Kn = 0.25mA/V2. 10k
280k
Find ID and VDS

R2 =
160k

Electronics
 Solution
1. VTH = 160 10 =
3.636 V 160 + 280
KVL at GS loop: VGS VTH + 0 = 0 VGS =
V
2. TH
Assume in saturation mode:
ID = Kn(VGS - VTN)2

So, ID = 0.669 mA

3. KVL at DS loop: VDS = VDD IDRD = 10 0.669 (10) = 3.31 V

4. VDS sat = VGS VTN = 3.636 2 = 1.636 V

So, VDS > VDSsat , therefore, assumption is correct!

Answer: ID = 0.669 mA and VDS = 3.31 V

Electronics
 MOSFET DC Circuit Analysis -
PMOS
Different notation:
VSG and VSD
Threshold Voltage = VTP

VG = VTH = R2 VDD
R1 + R2

Use KVL at GS loop:

VSG + 0 + VTH VDD = 0
VSG = VDD - VTH

Electronics
 MOSFET DC Circuit Analysis
- PMOS
Assume the transistor is biased in the saturation
region, the drain current:
ID = Kp (VSG + VTP)2
Calculate VSD:
Use KVL at DS loop:
VSD + IDRD - VDD = 0
VSD = VDD - IDRD
If VSD > VSD(sat) = VSG + VTP, then the transistor is biased in the
saturation region.
If VSD < VSD(sat), then the transistor is biased in the non-saturation
region.
Electronics
Calculate the drain current and source to drain voltage of a common
source circuit with an p-channel enhancement mode MOSFET.
Also find the power dissipation.
Assume that, VTP = -1.1V and Kp = 0.3 mA/V2
5V
Use KVL at SG loop:
VSG + 0 +2.5 5 = 0
VSG = 5 2.5 = 2.5 V
50 k
VSG > |VTP |

Assume biased in saturation mode:

50 k
7.5 k

Hence, ID = 0.3 ( 2.5 1.1)2 = 0.5888mA

Calculate VSD

Use KVL at SD loop:

VSD + IDRD 5 = 0
VSD = 5 - IDRD
Electronics
VSD = 5 0.5888 ( 7.5) = 0.584 V
 VSD sat = VSG + VTP = 2.5 1.1 = 1.4V
Hence, VSD < VSD sat. Therefore assumption is
incorrect. The transistor is in non-saturation mode!

ID = 0.3 2 ( 2.5 1.1) (5 IDRD) (5 IDRD)2

ID = 0.3 2.8 (5 7.5ID) (5-7.5ID)2

ID = 0.3 14 21ID (25 75ID + 56.25ID2)

ID = 0.536 mA

ID = 0.3 14 21ID -25 +75ID 56.25ID2

ID = 0.365
Electronics mA
56.25 I 2
50.67 I + 11 = 0
 ID = 0.536 mA ID = 0.365
mA

VSD = 5 IDRD = 0.98 V VSD = 5 IDRD = 2.26 V

VSD sat = VSG + VTP = 2.5 1.1 = 1.4V

0.98V < 1.4V 2.26V > 1.4V

Smaller than VSD sat : OK! Bigger than VSD sat : not OK

Answer: ID = 0.536 mA and VSD = 0.98V

Power dissipation = ID x VSD = 0.525 mW

Electronics
 LOAD LINE
Common source configuration i.e
source is grounded.
It is the linear equation of ID versus VDS
Use KVL
VDS = VDD IDRD
ID = -VDS + VDD
RD RD

Electronics
 ID (mA)

y-
intercept

Q-
ID POINTS VGS

VDS (V)
VDS x-
intercept

Electronics
 DC Analysis where source is NOT GROUNDED

For the NMOS transistor in the circuit below, the parameters are V TN =
1V and Kn=0.5mA/V2.

Electronics
 1. Get an expression for VGS in terms of ID

use KVL:

0 + VGS+ 1(ID) -5 +1
=0
VGS = 4 - ID
2. Assume in saturation

ID = 0.5 ( 4 - ID 1)2 = 0.5 ( 3 ID) 2

2ID = 9 6ID + ID2 ID = 1.354

ID 8ID + 9 = 0
2 Replace in VGS =
mA VGS 2.646 V
ID = 6.646 equation VGS= -2.
mA VGS = 4 - ID 646 V
Why choose VGS = 2.646 V ?
Electronics Because it is bigger than VTN
 3. Get VDS equation and use the value of ID
from step 2
Use KVL:
IDRD + VDS + IDRS 5 5 = 0
1.354 (2) + VDS + 1.354 10
=0 ID
VDS = 10 1.354 2.708 =
4.
5.938
Calculate
V VDS sat

VDS sat = VGS VTN = 2.646 1 = 1.646 V

5. Confirm your assumption ID

VDS > VDS sat CONFIRMED

Electronics