Cmos Nor, Deletion Load Nor Gate

Digital IC Design
Faculty-in-charge: Dr. Sitangshu Bhattacharya

Department of ECE
Indian Institute of Information Technology-Allahabad
Room No. 2221, CC-I
Telephone: 2131
Email: sitangshu@iiita.ac.in
Digital IC Design
Contents:
o MOS Transistor: Structure, External Bias, o Dynamic Logic Circuits Pass transistors, Voltage
Operation, Current-Voltage Characteristics, Bootstrapping, Synchronous Dynamic Circuit
Capacitances, Small Geometry Scaling Testing, Dynamic CMOS Circuit Techniques, High
performance Dynamic CMOS circuits
o MOS Inverters: Resistive Load Inverter, n-type
MOSFET load inverter, CMOS inverter o Semiconductor Memories DRAM, SRAM, Non-
volatile, Flash Memory, FRAM
o Switching Characteristics and Interconnect
Effects: Delay Time and constraints, Interconnect o Low Power CMOS Logic Circuits Low Power
parasitics, Interconnect delay calculation, Switching Design Switching Activity, Switched Capacitance,
power dissipation of CMOS inverters Adiabatic Logic Circuits
o Combinational MOS Logic Depletion Logic o BiCMOS Logic Circuits BJT, Dynamic behavior,
Circuits with nMOS loads, CMOS logic circuits, BiCMOS static behavior Switching Delay
CMOS transmission gates
o Chip I/O Circuits ESD protection, Output Circuit
o Sequential MOS Logic Bistable elements, SR Noise, On Chip Clock Generation and Distribution,
Latch, Clocked Latch with FF circuits, CMOS D- Latchup and its prevention
latch and Edge Triggered FFs
Reading Materials:
1. CMOS Digital Integrated Circuits Analysis and Design By S-Mo Kang and Y Leblebici
2. Digital Integrated Circuits: Analysis and Design By John E. Ayers
3. Digital Integrated Circuits: A Design Perspective By Anantha P. Chandrakasan,
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017 Borivoje Nikolic, and Jan M. Rabaey
Digital IC Design
Combinational MOS Logic

See Kang and Leblebici Book
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design
Two input depletion load NOR Gate

Digital IC Design

Calculation of VOH : Va and Vb are low

Digital IC Design

Calculation of VOH : Va and Vb are low

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Calculation of VOL : Threshold voltage of two transistors are identical
Possible cases for conduction path are:
1. Va = VOH Vb = VOL
2. Va = VOL Vb = VOH
3. Va = VOH Vb = VOH

Digital IC Design

For driver A ON case (i)

Digital IC Design

For driver A ON case (i)

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For each driver:

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For case (iii) when both of the drivers are ON:

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As VA = VB= VOH you can write :

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Thus,
Note that this VOL is lower that the previous two VOLs.

Digital IC Design
N- input depletion load NOR Gate

Digital IC Design
N- input depletion load NOR Gate (Equivalent ckt.)

Digital IC Design
Two input depletion load NOR Gate: Transients

Digital IC Design
Two input depletion load NOR Gate: Transients

Digital IC Design
Two input depletion load NAND Gate
Note: Substrate bias effect here

as source is not at 0V

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When both drivers are high (VOH):


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If
Then since
VOL = VDs, A + VDS,B as source is not at 0V

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If we assume VT,A = VT,B = VT0
The linear driver currents:

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Since

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Since
Two n-MOS in series with same gate

Final drain current: voltage behaves like one nMOS with
keq= 0.5 kdriver
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N- input depletion load NAND Gate

Digital IC Design
Two- input depletion load NAND Gate: Transient
When VA = VOH and

VB changes from
VOH to VOL

Digital IC Design
Two- input depletion load NAND Gate: Transient
When VB = VOH and

VA changes from
VOH to VOL

Digital IC Design
CMOS NOR Gate
Series connection
Parallel connection

Digital IC Design
CMOS NOR Gate
Series connection
Parallel connection
Either n-MOS network is ON and pMOS network is OFF, or the pMOS network is ON and nMOS network is OFF

Digital IC Design
CMOS NOR Gate
Series connection
Parallel connection
When either one or both inputs are high nMOS ON VOUT = 0V

Digital IC Design
CMOS NOR Gate
Series connection
Parallel connection
When both inputs are low nMOS OFF pMOS ON VOUT = VDD

Digital IC Design
CMOS NOR Gate
Series connection
Parallel connection
When both inputs are low nMOS OFF pMOS ON VOUT = VDD VOL = 0V
VOH = VDD
Digital IC Design
CMOS NOR Gate
Let us have
all aspect ratios to be same
Substrate bias of pMOS is negligible.

Digital IC Design
CMOS NOR Gate
The output voltage = input voltage at the switching threshold

Linear
Saturation
saturation

Digital IC Design
CMOS NOR Gate

Linear
Saturation
saturation

Digital IC Design
CMOS NOR Gate

Linear
For nMOS: Saturation
saturation

Digital IC Design
CMOS NOR Gate

Linear
For nMOS: Saturation
Therefore the switching threshold:
saturation

Digital IC Design
CMOS NOR Gate

Linear
For pMOS: Saturation
saturation

Digital IC Design
CMOS NOR Gate

Linear
As
saturation
Thus:

Digital IC Design
CMOS NOR Gate

Linear
As
saturation
Thus:
Hence:

Digital IC Design
CMOS NOR Gate
Difference between switching threshold of CMOS and NOR

inverter Linear
Saturation
For NOR:
saturation
For CMOS:

Digital IC Design
CMOS NOR Gate
Difference between switching threshold of CMOS and NOR

inverter Linear
Saturation
For NOR:
saturation
For CMOS:
for

Digital IC Design
CMOS NOR Gate: Equivalent Ckt.

Digital IC Design
CMOS NAND Gate

Digital IC Design
CMOS NAND Gate

Digital IC Design
CMOS NAND Gate

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MOS Layout

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CMOS Layout

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CMOS NOR2 Layout

Digital IC Design
CMOS NOR2 Layout
CMOS NOR2 Stick Diagram

Digital IC Design
CMOS NAND2 Layout

Cmos Nor, Deletion Load Nor Gate

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Digital IC Design

Faculty-in-charge: Dr. Sitangshu Bhattacharya

Combinational MOS Logic

Combinational MOS Logic

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Possible cases for conduction path are:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Possible cases for conduction path are:

For driver A ON case (i)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Possible cases for conduction path are:

For driver A ON case (i)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

For each driver:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

For case (iii) when both of the drivers are ON:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

For case (iii) when both of the drivers are ON:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

For case (iii) when both of the drivers are ON:

As VA = VB= VOH you can write :

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

N- input depletion load NOR Gate

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

N- input depletion load NOR Gate (Equivalent ckt.)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate: Transients

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NOR Gate: Transients

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Combinational MOS Logic

Two input depletion load NAND Gate

Note: Substrate bias effect here