Digital Logic Design (Lecture 15)

Muhammad Umer
Lecturer
Institute of Management Sciences
 Objectives
Discuss Sequential logic
Synchronous
Asynchronous

Discuss Latch
SR Latch

Discuss Flip Flop

SR Flip-Flop
D Flip-Flop
JK and T Flip-Flop

Triggering of Flip Flops

Master Slave Flip Flop
Edge Triggered Flip Flop
 Sequential Logic
Sequential logic is a type of logic circuit whose output
depends not only on the present value of its input signals
but on the past history of its inputs

Sequential logic has state (memory) while combinational

logic does not, or in other words, sequential logic is
combinational logic with memory
 Digital sequential logic circuits are divided into 2
types:
Synchronous sequential logic circuits
Asynchronous sequential logic circuits

Synchronous sequential circuits: State of

the device changes only at discrete times in
response to a clock signal

Asynchronous circuits: State of the device

can change at any time in response to changing
inputs
 Latch
Latch continuously checks for inputs & changes the
output whenever there is a change in input

Latch is a building block of the flip flop

Similarly Flip Flop checks input, but changes the output

determined by clock. Even though if inputs are changed,
it may not change the output at the same time

Latch can be constructed from two NAND gates or two

NOR gates
SR Latch using NOR Gate
SR Latch using NAND Gate
 The cross-coupled connection from the output of
one gate to the input of the other gate constitutes
a feed back path. For this reason, the circuits are
classified as Asynchronous sequential circuits

Each latch has two outputs (Q and Q) , and two

inputs (set and reset)

This type of latch is sometimes called SR latch (R

and S are the first letters of two input names)
 Analysis of SR Latch using NOR Gate
Assume, set input is 1 and the reset input is
0
1
One input to Gate 2 is 1 so output Q must
be 0, this makes both inputs of Gate 1 as 0 2
and Q is 1

When the set input is returned to 0, outputs

remains same (Q is 1), leaving one
input of gate 2 at 1

That causes output Q to stay at 0, which

leaves both inputs of gate 1 at 0, so that
output Q is 1
 When 1 is applied to both the inputs, both Q and Q
outputs go to 0. This condition violates the fact that Q
and Q are compliment of each other. Condition when
both inputs are 1 is normally avoided

Flip Flop/ Latch has two useful states:

Q = 1 and Q =0; set state (1-state)
Q = 0 and Q =1; clear state/ reset state (0-state)

When both inputs are initially 0 and in set state if 1 is

applied to set input or in clear state if 1 is applied to
reset input, both leaves the outputs unchanged
 Analysis of SR latch using NAND Gate
Operates with both inputs normally at 1
unless the state of the latch has to be changed

Application of momentary 0 to set input

causes output Q to go to 1 and Q to go to
0,thus putting the latch into set state

When set input returns to 1, a momentary 0

to the reset input causes a transition to clear
state

Condition when both inputs are o is

normally avoided
 Flip Flop
A flip-flop is a circuit that has two stable states
and can be used to store state information

Flip Flop can maintain a binary state indefinitely

(as long as power is delivered to the circuit)
until directed by an input signal (input and
clock) to switch states
 Flip Flop Types
Major differences among various types of flip-
flops are in the number of inputs they possess
and in the manner in which the inputs affect the
binary state

Common types are:

SR Flip-Flop
D Flip-Flop
JK and T Flip-Flop
 SR Flip Flop
Operation of basic flip flop can be modified by
providing additional control input that
determines when state of input is to be changed

SR flip flop with Clocked Pulse

 SR flip-flop is: Basic flip-flop circuit + two
additional NAND gates + clock pulse generator

Clock Pulse: Enable signal for the two inputs

CP is 0 : output of the gates 3 and 4 remains at
logic 1 until CP is 0.It is quiescent (inactive)
condition of the flip-flop

CP is 1 : Information from S and R is allowed to

reach the output only when clock pulse goes to 1
 Working
Set State: The set state is reached at S=1, R=0 and CP=1

So when S=1, R=0 and CP=1, both the inputs to the gate 3
are 1 and hence its output is 0
This information (i.e.) 0 is
passed to gate 1. Since one of
the inputs of gate 1 is 0, so
Q=1 and As R=0, so Q=0 RS flip flop with Clocked Pulse

Conclusion: When S=1, R=0 and CP=1 => Q=1 and Q=0
 Reset State: Now to change to reset state, the inputs must
be S=0, R=1 & CP=1. The observed outputs are Q=0 & Q=1

When the clock pulse returns to zero, the circuit remains in

its previous state. This is applicable to both Set and Clear
states

Now when CP=1, inputs S=0 & R=0, that is when both the
inputs are 0, the state of the circuit does not change

When CP=1, S=1 & R=1, an indeterminate condition occurs

because both the outputs Q and Q remain at 1. This is not
possible because both the outputs are complementary to
each other, so it is better to avoid this condition during
practice
 D Flip Flop
D flip-flops are used to eliminate the
indeterminate state that occurs in SR flip-flop
i.e. R and S are never equal to 1 at the same
time

D Flip Flop : Logic Diagram

 Two inputs : D and CP

D input of the flip-flop is directly given to S input and the

complement of this value is given as the R input

Similar to RS flip-flop, the outputs of gate 3 and 4 remain

at logic 1 until the clock pulse applied is 0, the value of
D wont affect the circuit until CP is in 0

The value of D is sampled only when CP goes from 0 to

1

When CP changes to 1, the value of D is sampled and the

information is passed to the output
 Working
Set State: CP=1 and D=1, the output of gate 3 goes
to 0 and this makes the output Q=1 and Q=0

Reset State: When CP=1 and D=0, the output is Q

=1 and Q=0

Since both S and R are given complementary

values, they can never be 1 at the same time. Thus
we can avoid the indeterminate state that occurs in
RS flip-flop

When CP returns to zero, the previous state of the

D Flip Flop : Logic Diagram
output is maintained (or) the output does not
change its state unless it is enabled again by clock
pulse

This Flip-flop is sometimes called Gated D-latch

 JK Flip Flop
JK (Jack Kilby) flip-flop is a refinement of SR
flip-flop with two AND gates which are
augmented to it

Logic Diagram : JK Flip Flop

 Two inputs of JK flip-flop are J
(set) and K (reset)

Q is AND with K and CP. This

arrangement is made so that the
flip-flop is cleared during a clock
pulse only if Q was previously 1
Logic Diagram : JK Flip Flop
Q is AND with J and CP, so that
the flip-flop is cleared during a
clock pulse only if Q was
previously 1
 Working
J=K=0
CP has no effect on the output and the
output of the flip-flop is the same as its
previous value

J=0, K=1
When J=0, the output of the AND gate
corresponding to J becomes 0 i.e. S=0 Logic Diagram : JK Flip Flop
and R=1. Therefore Q becomes 1. This
condition will reset the flip-flop. This
represents the RESET state of flip-flop
 J=1, K=0
AND gate corresponding to K becomes 0
i.e. S=1 and R=0.Q becomes 1 and this will
set the Flip-flop. This represents the SET
state of Flip-flop

J=K=1
For CP=1 above condition will cause the
output to complement again and again. This
complement operation continues until the
clock pulse goes back to 0
Logic Diagram : JK Flip Flop
Since this condition is undesirable, we have
to find a way to eliminate this condition.

This undesirable behavior can be eliminated

by Edge triggering of JK flip-flop or by
using master slave JK Flip-flops
Characteristic Equation and Table
 T Flip Flop
T flip-flops are single input version of JK flip-flops and
are obtained by connecting both inputs J and K together

These flip-flops are called T flip-flops because of their

ability to complement its state (i.e.) Toggle

T Flip Flop
 Working
T flip-flop has only one input along with Clock pulse

When T=1 and CP=1, the flip-flop complements its

output, regardless of the present state of the flip-
flop. In this case the next state is the complement of
the present state

When T=0, there is no change in the state of the

flip-flop (i.e.) the next state is same as the present
state of the flip-flop
Characteristic Equation and Table

Characteristic table Characteristic Equation

From the characteristic table and characteristic

equation it is quite evident that when T=0, the
next sate is same as the present state
 Triggering of Flip Flops
The state of a flip-flop is changed by a momentary change
in the input signal. This change is called a trigger and
the transition it causes is said to trigger the flip-flop

The basic circuits of flip flop using NAND or NOR

gates require an input trigger defined by a change in
signal level

This level must be returned to its initial level before a

second trigger is applied. Clocked flip-flops are triggered
by pulses
 The feedback path between the combinational circuit
and memory elements can produce instability if the
outputs of the memory elements (flip-flops) are changing
while the outputs of the combinational circuit that go to
the flip-flop inputs are being sampled by the clock pulse

A way to solve the feedback timing problem is to make

the flip-flop sensitive to the pulse transition rather than
the pulse duration
 The clock pulse goes through two signal
transitions: from 0 to 1 and then return from
1 to 0

Definition of clock pulse signal

Positive transition is defined as the positive edge

and the negative transition as the negative edge
 The clocked flip-flops (as previously discussed)
are triggered during the positive edge of the
pulse, and the state transition starts as soon as
the pulse reaches the logic 1 level

If the other inputs change while the clock is still

1, a new output state may occur

If the flip-flop is made to respond to the positive

(or negative) edge transition only, instead of the
entire pulse duration, then the multiple-
transition problem can be eliminated
 Master-Slave Flip Flop

A master-slave flip-flop is constructed from two

separate flip-flops

One circuit serves as a master and the other as a

slave
 Master Slave Flip Flop : SR Flip Flop
The master flip-flop is enabled on the positive edge of the clock pulse CP and
the slave flip-flop is disabled by the inverter

The information at the external R and S inputs is transmitted to the master flip-
flop

When the pulse returns to 0, the master flip-flop is disabled and the slave flip-
flop is enabled

The slave flip-flop then goes to the same state as the master flip-flop

Logic Diagram Master Slave Flip Flop

 Timing Relationship
It is assumed that the flip-flop is in the clear state prior
to the occurrence of the clock pulse

The output state of the master-slave flip-flop occurs on

the negative transition of the clock pulse

Timing relationship in a master slave flip-flop

 Some master-slave flip-flops change output state
on the positive transition of the clock pulse by
having an additional inverter between the CP
terminal and the input of the master
 Edge Triggered Flip Flop
Another type of flip-flop that synchronizes the state changes
during a clock pulse transition is the edge-triggered flip-flop

When the clock pulse input exceeds a specific threshold level,

the inputs are locked out and the flip-flop is not affected by
further changes in the inputs until the clock pulse returns to 0
and another pulse occurs

Some edge-triggered flip-flops cause a transition on the positive

edge of the clock pulse (positive-edge-triggered), and others on
the negative edge of the pulse (negative-edge-triggered)
 Positive Edge Triggered S-R Flip Flop
The operation and truth table for a negative edge-
triggered flip-flop are the same as those for a positive
except that the falling edge of the clock pulse is the
triggering edge
 Graphical Symbol

Negative Edge D Flip Flop

(Similarly for all flip flops)

Positive Edge Triggered