Digital Logic Design (Lecture 14)

Muhammad Umer
Lecturer
Institute of Management Sciences
 Objectives
Discuss PLA

Discuss PAL
 PLA (Programmable Logic Array)
Programmable logic array (PLA) is programmable logic
device used to implement combinational logic circuits

PLA has a set of programmable AND gate planes, which

link to a set of programmable OR gate planes, which can
then be conditionally complemented to produce an
output

This layout allows for a large number of logic functions

to be synthesized in the SOP (sometimes POS)
 Conventions
The conventional symbols drawn with
multiple lines showing the fuse connected with
the inputs of the gate
 Array logic symbol uses a single horizontal line
connected to the gate input and multiple vertical lines to
indicate the individual inputs.

Each intersection between a vertical line and the

common horizontal line has a fused connection.

In array logic symbol, the AND gate has four inputs

connected through fuses:

In a similar fashion we can draw the array logic for the

OR gate or any type of multiple input gate
 PLA Example
Lets suppose we want to implement the given
functions from 3- input PLA
3 Input PLA
Solution
 In the Logic Diagram given above:
Inputs: A, B and C, where each input goes
through a buffer and an inverter

Each input and its compliment are connected to

the inputs of each AND gate as indicated by the
intersections between the vertical and
horizontals lines

Output of And gates are connected to the inputs

of each OR gate
 Function Table

Input side: Output side

1 = Variable in term 1 = Term connected to output
0 = Complimented in term - = No connection to output
- = Doest not participate
 PAL (Programmable Array Logic)
Programmable Array Logic (PAL) is a family
of programmable logic device semiconductors
with a fixed OR array and a programmable
AND array used to implement logic functions in
digital circuits

PAL is easier to program as only AND gates are

programmed, but since the OR array is fixed, it
is less flexible than a PLA device
PAL with 4 inputs , 4
outputs and three
wide AND-OR
structure
 In the logic diagram given above:
Inputs: I1, I2, I3 and I4, each input has a buffer-inverter
gate and each output is generated by a fixed OR gate

4 sections in the unit. Each being composed of a 3 wide

AND-OR array

Each AND gate has 10 programmable input

connections, shown by 10 vertical lines intersecting
each horizontal line

One of the output is connected to buffer-inverter gate

and then fed back into two inputs of the AND gates
 Lets suppose we want to implement the given
functions from 4- input PAL

w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = ABC + ABCD+ACD + ABCD
= w + ACD + A BCD

Note that the function z has 4 product terms, the

logical sum of two of these terms is equal to w. By
using w, it is possible to reduce the number of terms
for z from 4 to 3
 PAL Boolean Function
Boolean functions must be simplified to fit into
each section

Unlike PLA, product term cannot be shared among

two or more OR gates. Therefore, number of
product terms in each section is fixed

If the number of terms in the function is too large,

it may require to use two boolean functions to
make one function
Boolean Table
Figure shows fuse Map
for PAL as specified in
previous table