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 The ARM Architecture

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
TM
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 ARM Ltd

 Founded in November 1990

 Spun out of Acorn Computers

 Designs the ARM range of RISC processor cores

 Licenses ARM core designs to semiconductor
partners who fabricate and sell to their customers.
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the

design-in of the ARM architecture
 Software tools, boards, debug hardware, application
software, bus architectures, peripherals etc

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 ARM Partnership Model

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 ARM Powered Products

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 Intellectual Property

 ARM provides hard and soft views to licencees

 RTL and synthesis flows
 GDSII layout
 Licencees have the right to use hard or soft views of the IP
 soft views include gate level netlists
 hard views are DSMs
 OEMs must use hard views
 to protect ARM IP

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 Development of the
ARM Architecture

Improved
Jazelle
Halfword
4 ARM/Thumb 5TE
and signed Interworking Java bytecode 5TEJ
1 halfword /
CLZ execution
byte support
System SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 mode
DSP multiply-
SA-1110 ARM7EJ-S ARM1026EJ-S
accumulate
instructions
3 ARM1020E SIMD Instructions
Thumb
instruction 4T Multi-processing
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set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E-S
Unaligned data
ARM720T ARM940T ARM966E-S support ARM1136EJ-S

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 ARM7TDMI Processor Core
 Current low-end ARM core for applications like digital mobile phones
 TDMI
– T: Thumb, 16-bit compressed instruction set
– D: on-chip Debug support, enabling the processor to halt in response to a
debug request
– M: enhanced Multiplier, yield a full 64-bit result, high performance
– I: EmbeddedICE hardware
 Von Neumann architecture
 3-stage pipeline

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 ARM7TDMI Processor Core

 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two
bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two

instruction sets
 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set

 Jazelle cores can also execute

Java bytecode

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 Processor Modes

 The ARM has seven basic operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 Supervisor : entered on reset and when a Software Interrupt

instruction is executed

 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user mode

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 The Registers

 ARM has 37 registers all of which are 32-bits long.

 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers

 The current processor mode governs which of several banks is

accessible. Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr

Privileged modes (except System) can also access

 a particular spsr (saved program status register)

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 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

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 Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V U n
f s
 Condition code flags
 N = Negative result from ALU
 Z = Zero result from ALU
 C = ALU operation Carried out
 V = ALU operation oVerflowed
 Sticky Overflow flag - Q flag
 Architecture 5TE/J only
 Indicates if saturation has occurred
d e f i n e d I F T mode
x c
 Interrupt Disable bits.
 I = 1: Disables the IRQ.
 F = 1: Disables the FIQ.
 T Bit
 Architecture xT only
 T = 0: Processor in ARM state
 T = 1: Processor in Thumb state

 Mode bits
 J bit  Specify the processor mode
 Architecture 5TEJ only
 J = 1: Processor in Jazelle state

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 Program Counter (r15)

 When the processor is executing in ARM state:

 All instructions are 32 bits wide
 All instructions must be word aligned
 Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

 When the processor is executing in Thumb state:

 All instructions are 16 bits wide
 All instructions must be halfword aligned
 Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

 When the processor is executing in Jazelle state:

 All instructions are 8 bits wide
 Processor performs a word access to read 4 instructions at once

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 Exception Handling

 When an exception occurs, the ARM:

 Copies CPSR into SPSR_<mode>
 Sets appropriate CPSR bits
 Change to ARM state 0x1C FIQ
 Change to exception mode
0x18 IRQ
 Disable interrupts (if appropriate)
0x14 (Reserved)
 Stores the return address in LR_<mode>
 Sets PC to vector address 0x10 Data Abort
0x0C Prefetch Abort
 To return, exception handler needs to: 0x08 Software Interrupt
 Restore CPSR from SPSR_<mode>
0x04 Undefined Instruction
 Restore PC from LR_<mode>
0x00 Reset
This can only be done in ARM state. Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family
devices

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 Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM

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 AMBA
Arbiter Reset

ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External

Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller

AHB or ASB APB

System Bus Peripheral Bus

 AMBA  ACT
 Advanced Microcontroller Bus Architecture  AMBA Compliance Testbench
 ADK
 Complete AMBA Design Kit  PrimeCell
 ARM’s AMBA compliant peripherals

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 The RealView Product Families

Compilation Tools Debug Tools Platforms

ARM Developer Suite (ADS) – AXD (part of ADS) ARMulator (part of ADS)
Compilers (C/C++ ARM & Thumb), Trace Debug Tools Integrator™ Family
Linker & Utilities
Multi-ICE
Multi-Trace

RealView Compilation Tools (RVCT) RealView Debugger (RVD) RealView ARMulator ISS
(RVISS)
RealView ICE (RVI)
RealView Trace (RVT)
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 ARM Debug Architecture
Ethernet

Debugger (+ optional
trace tools)

JTAG port Trace Port

 EmbeddedICE Logic
 Provides breakpoints and processor/system
access
TAP
 JTAG interface (ICE) controller
 Converts debugger commands to JTAG
ETM
signals
EmbeddedICE
 Embedded trace Macrocell (ETM) Logic
 Compresses real-time instruction and data
access trace
 Contains ICE features (trigger & filter logic)
 Trace port analyzer (TPA) ARM
 Captures trace in a deep buffer core

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 LPC 2478

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R
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 LPC2478 Memory Map

Ethernet w/DMA & USB (OTG, OHCI w PHY)

4.0 GB 0xFFFF FFFF
AHB Peripherals
0xF000 0000
Timers, PWM, I2C, SPI, I2S, UARTs, CAN,
APB Peripherals 0xE000 0000 SSP, DAC, ADC
0xDFF FFFF

External Static and

Dynamic Memory • Memory mapped I/O
• Flash sector sizes from 4 kB to 32 kB
0x8000 0000
• Flash = 100,000 write- erase cycles
2.0 GB Boot Block • Boot Block supports
Reserved for on-chip • In-Application Programming
Static Ram and • In-System Programming
Special Registers
0x4000 0000

Flash Memory
0.0 GB 0x0000 0000

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 LPC2478
System Functions

• Internal Reference Clock (IRC)

• External Clock ( X1/X2)
• Real Time Clock (RTXC1/RTXC2)
• Phase-Locked Loop
• Peripheral & CPU Clock
• Power Control For Each Peripheral
• Power-On/Reset
• Brown-Out Detection

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 LPC2478
Clock Subsystem

CCLK & PLLCLK

 System clock (PLLCLK) can be USB
Clock
usbclk
(48 MHz)
USB Block
derived from three sources
Divider
Main
Oscillator

Main crystal (1MHz to 20MHz)

PLL CPU
 pllclk
Clock
cclk
ARM7TDMI-S
Divider

 Internal RC oscillator (IRC) system

clock select
Bypass
Synchro- Ethernet
25 or
50 MHz
External
nizer Ethernet
Block
 Factory Trimmed to +/-1% Internal
R/C
PHY

Oscillator Other AHB

Real time clock (RTC)
wdclk Watchdog
 Timer Peripherals
Perpipheral
Clock

CPU clock (CCLK) can be separate

Generator
 watchdog
clock select pclk APB
Peripherals

from the APB peripherals RTC

Prescaler

 CCLK can be higher or lower than the RTC

rtcclk Real Time
Clock

APB peripherals Oscillator

RTC clock
select

 Independent peripheral clocks

 Watchdog Timer has a separate
clock selector mux

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 LPC2478
Clock Subsystem
usbclk
USB
(48 MHz)
Clock
Divider USB Block
Main
Oscillator
PLL CPU
pllclk cclk
Clock ARM7TDMI-S
Divider

system Bypass 25 or
clock select External
Synchro- Ethernet 50 MHz
nizer Ethernet
Block
Internal PHY
R/C
Oscillator wdclk Watchdog Other AHB
Timer Peripherals
Perpipheral
Clock
watchdog Generator
clock select pclk APB
Peripherals
RTC
Prescaler

rtcclk Real Time

RTC Clock
Oscillator
RTC clock
select

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 Independent Peripheral Clocks (PCLK)

PCLKSELx allows
four individual clock
selections for each
peripheral

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 LPC2478
Power Control

 Idle Mode – clock to the core is stopped

 Execution of instructions is suspended until an interrupt or reset occurs
 Sleep Mode – PLL is turned off
 Processor state and registers, peripheral registers and RAM values are
preserved
 Flash is left in standby mode
 LPC2478 resumes operation when certain types of interrupts not requiring a
clock occur or a reset happens
 Power down Mode – All clocks except for the RTC* are turned off
 Flash memory is turned off
 Minimal power consumption
 LPC2478 wakes up when certain types of interrupts not requiring clock occur or
a reset
* RTC clock pins and VBAT pin connected and RTC mode enabled

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 Power Control for each Peripheral

•The PCONP Register determines if a peripheral is switched on or off

• 0 = Off
• 1 = On

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 I/O Pin Selection
 Each I/O pin can be used for one of several functions

Example:
P0.2 = TXD0 (UART0 TXD)
P0.3 = RXD0 (UART0 RXD)
Other pin selects are GPIO
PINSEL0 =0x00000050

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